sta381bw STMicroelectronics, sta381bw Datasheet - Page 90

• Manufacturer Part Number: sta381bw
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

Register description: New Map
6.29
90/168
Figure 26. Short-circuit detection timing diagram (no short detected)
In
in clock cycles, where the clock frequency is defined as in section
clock
carrying the status of the previous EAPD 0->1 toggling (to be noted that after reset this state
is meaningless since no EAPD transition occurs). The GND-related SHOK bits are updated
as soon as the gnd test is completed, the VCC bits are updated after vcc test is completed,
and the SOUT bit is updated after the shorted output test is completed. The gnd test, vcc
test and output test, are always run (if the SHEN bit is active and EAPD toggled to ‘1’), and
only if both tests are successful (no short) the do bridge outputs leave the tristate (indicated
by dotted lines in the figure). If one of the three tests (or all) fail, the power bridge outputs
are kept in the tristate until the procedure is restarted with a new EAPD toggling.
In this figure EAPD is intended to be bit 7 of register 0x05.
Extended coefficient range up to -4...4 (address 0x5A)
Biquads from 1 to 7 have in the STA381BW the possibility to extend the coefficient range
from [-1,1) to [-4..4) which allows the use of high shelf filters that may require a coefficient
dynamic greater in absolute value than 1.
Three ranges are available, [-1;1) [-2;2) [-4;4). By default, the extended range is activated.
Each Biquad has its independent setting according to the following table.
CEXT_B4[1]
Figure 26
reserved
GNDSH]
OUTSH]
VCCSH
OUT1A
OUT1B
OUT2A
OUT2B
D7
D7
1
0
EAPD
select. The gray color is used for the short status bits to indicate that the bits are
the short protection timing diagram is shown. The time information is expressed
CEXT_B4[0]
reserved
D6
D6
0
0
CEXT_B3[1]
CEXT_B7[1]
cycles
44
D5
D5
Start gnd test
1
1
Doc ID 018835 Rev 2
50005 cycles
CEXT_B3[0]
CEXT_B7[0]
D4
D4
0
0
Start vcc test
CEXT_B2[1]
CEXT_B6[1]
50005 cycles
D3
D3
1
1
Start out test
CEXT_B2[0]
CEXT_B6[0]
D2
D2
0
0
TBD cycles
Section 6.13.1: Master
CEXT_B1[1]
CEXT_B51]
1cycle
End of Short test
D1
D1
1
1
STA381BW
CEXT_B1[0]
CEXT_B5[0]
D0
D0
0
0