saa6713ah NXP Semiconductors, saa6713ah Datasheet - Page 16

• Manufacturer Part Number: saa6713ah
• Description: Xga Analog Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

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Note
1. X = don’t care.
Table 8 ADC configuration registers (page 1)
SYNC_DIS
PLL programming: 20H to 29H
CD_PLL_CTRL
CD_PLL_P_HI
CD_PLL_P_LO
CD_PLL_HI
CD_PLL_LO
CD_LPLL_HI
CD_LPLL_LO
CD_LPLL_PHA
CD_LPLL_PD
CD_PLL_LOCK
Interface timing: 34H and 35H
IT_CTRL
IT_PLL
ADC programming: 00H to 06H
ADC_CTRL
ADC_R_BRI
ADC_R_CON
ADC_G_BRI
REGISTER
REGISTER
19H W
23H W
24H W
ADR R/W
20H W
21H W
22H W
25H W
26H W
27H W
28H W
29H R
34H W
35H W
ADR R/W
00H W
01H W
02H W
03H W
00H
00H
00H
00H
00H
00H
00H
000 0000
010 000
100 0000
RESET
RESET
00 0000
00 0000
0 0000
1111
XXX
000
11
pll_pre_div[15:8]
pll_pre_div[7:0]
pll_n_div[7:0]
line_pll_n_div[7:0]
adc_red_brightness[7:0]
adc_red_contrast[7:0]
adc_green_brightness[7:0]
D7
D7
reserved
line_pll_
hs_pol
phase_
auto
D6
D6
mdd_cs_
sog_en
line_pll_
vs_pol
pll_m_div[1:0]
line_pll_m_div[1:0]
phase_
select
D5
D5
mdd_hs_
regen_on
line_pll_en
line_pll_phase[4:0]
pd_pll_phase[4:0]
D4
D4
pll_n_div[11:8]
line_pll_n_div[11:8]
pll_coast_
pol
D3
D3
reserved
pll_src
phase_
inlock
pll_pon_pol llpll_coast_
sog_vs_
disable
D2
D2
iif_cs_sog_
en
pll_pre_
div_en
pll_inlock
adc_pon_
pol
pol
reserved
D1
D1
iif_hs_
regen_on
pll_en
llpll_inlock
bigger_
out_pol
llpll_pon_
pol
sync_on_
green_en
D0
D0