saa6713ah NXP Semiconductors, saa6713ah Datasheet - Page 85

• Manufacturer Part Number: saa6713ah
• Description: Xga Analog Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.16.12 A
Every output pin, except pin PWM, can be delayed. The delay increment is 0.36 ns. The programming value is 5-bit wide
(see Table 59).
Table 59 Data to output mapping
7.16.13 P
A pulse width modulated signal can be generated for
brightness control of the panel. The pulse width and the
pre-divider value can be programmed. The PWM can be
synced with the h-gate. The logical polarity can be
inverted.
The PWM runs with the system clock and can be divided
by the pre-divider. A period depends on 256 cycles.
The configuration registers for the PWM are OI_PWM0
and OI_PWM1.
7.16.14 R
A hardware reset forces all true bidirectional pins (PAx,
PBx, PCx, VCLK, VSYNC and SDA) to input. Their output
functionality must be explicitly invoked by software.
CSG2/A0 and CSG4/A1 are input during the hardware
reset for latching in the configuration data and switched to
output immediately after hardware reset.
2004 Apr 05
OI_INVA_DEL
OI_INVB_DEL
OI_PAD
OI_PBD
OI_PCD
OI_PDD
OI_PED
OI_PFD
OI_CTRL1
OI_G0BD
OI_G1BD
OI_G2D
OI_G3D
OI_G4D
OI_G5D
OI_G6D
OI_G7D
OI_G8D
OI_G9D
XGA analog input flat panel controller
DJUSTABLE OUTPUT DELAYS
ULSE WIDTH MODULATION
ESET BEHAVIOUR
REGISTER
inversion_A_pin_delay[4:0]
inversion_B_pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
PCLK_pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
pin_delay[4:0]
BIT
85
8
The SAA6713AH has built-in logic and 5 dedicated pins to
support boundary scan testing which allows board testing
without special hardware (nails). The SAA6713AH follows
the “IEEE Std. 1149.1 - Standard Test Access Port and
Boundary-Scan Architecture” set by the Joint Test Action
Group (JTAG) chaired by Philips.
The 5 special pins are: Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).
The Boundary Scan Test (BST) functions BYPASS,
EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all
supported (see Table 60). Details about the
JTAG BST-TEST can be found in the specification
“IEEE Std. 1149.1” .
A file containing the detailed Boundary Scan Description
Language (BSDL) description of the SAA6713AH is
available on request.
BOUNDARY SCAN TEST
INVA
INVB
PA
PB
PC
PD
PE
PF
PCLK
CSG0
CSG1
CSG2
CSG3
CSG4
CSG5
CSG6
CSG7
CSG8
CSG9
OUTPUT
SAA6713AH
Product specification