x96012 Intersil Corporation, x96012 Datasheet

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... Data Sheet Universal Sensor Conditioner with Dual Look-up Table Memory and DACs The X96012 is a highly integrated bias controller, which incorporates two digitally controlled Programmable Current Generators, temperature compensation with dedicated look-up tables, and supplementary EEPROM array. All functions of the device are controlled via a 2-wire digital serial interface ...

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... In both cases, the voltage at this pin is the reference for the A/D converter and the two D/A converters. Current Generator 2 Output. This pin sinks or sources current. The magnitude and direction of the current is fully 14 I2 programmable and adaptive. The resolution is 8 bits. 2 X96012 VOLTAGE LOOK-UP MUX TABLE 2 ADC LOOK-UP ...

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... Input TSenseRange Temperature Sensor Range I Current from pin VSS R 3 X96012 Thermal Information Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C Temperature While Writing to Memory . . . . . . . . . . . . 0°C to +70°C Voltage on VCC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V Voltage on any other Pin . . . . . . . . . . . . . . . . . . . . . . . . VCC ± ...

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... Undershoot on D/A Converter Data Byte UNDER Transition Rise Time on D/A Converter Data Byte rDAC Transition; 10% to 90% 4 X96012 and V . 400kHz TTL input at SCL. SDA pulled TEST CONDITIONS Figure 11 6 /(1.21V x +140°C). (See “Electrical Specifications” table starting on page 3 for standard conditions). ...

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... DNL errors starting from code 00h to the code where the INL measurement is desired. The measured transfer curve is adjusted for Offset and Fullscale errors before calculating INL. 5 X96012 (See “Electrical Specifications” table starting on page 3 for standard conditions). TEST CONDITIONS See Figure 8. Bits I1FSO[1:0] ¦ ...

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... STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle the WC minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. 17. The minimum frequency requirement applies between a START and a STOP condition. 6 X96012 TEST CONDITIONS See “2-Wire Interface Test Conditions” on page 6 See Figures 1, 2 and 3. ...

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... F SCL t SU:DAT t SU:STA t HD:STA SDA IN SDA OUT START SCL SDA IN WP SCL SDA 8TH BIT OF LAST BYTE 7 X96012 HIGH LOW R t HD:DAT FIGURE 1. BUS TIMING CLK SU:WP HD:WP FIGURE 2. WP PIN TIMING ACK STOP CONDITION FIGURE 3. NON-VOLATILE WRITE CYCLE TIMING ...

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... All bits in Control register 6 always power-up to the logic state “0”. All bits in Control registers 0 through 5 power-up to the logic state value kept in their corresponding nonvolatile memory cells. The nonvolatile bits of a register retain their stored values even when the X96012 is powered down, then ° +100 C). The powered back up ...

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... When bit L2DAS (bit 6 in Control register 5) is set to “1”, LUT2 is addressed by these six bits, and it is not addressed by the output of the on-chip A/D converter. When bit L2DAS is set to “0”, these six bits are ignored by the X96012. See Figure 10. A value between 00h (00 these register bits, to select the corresponding row in LUT2 ...

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... WRITE ENABLE LATCH 0: WRITE DISABLED 1: WRITE ENABLED ADC OUTPUT 87h AD7 AD6 VOLATILE REGISTERS IN BYTE ADDRESSES 88h THROUGH 8Fh ARE RESERVED. FIGURE 4. CONTROL AND STATUS REGISTER FORMAT 10 X96012 NV1234 ADCfiltOff ADCIN VRM ADC ADC INPUT VOLTAGE FILTERING 0: INTERNAL REFERENCE ...

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... The WEL bit is enabled by writing 10000000 Control register 6. Once enabled, the WEL bit remains set to “1” until the X96012 is powered down, and then up again, or until it is reset to “0” by writing 00000000 A Write operation that modifies the value of the WEL bit will not cause a change in other bits of Control register 6 ...

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... The A/D converter input voltage range (VIN to V(VRef). A/D Converter Input Select The input signal to the A/D converter on the X96012, may be the output of the on-chip temperature sensor external source via the VSense pin. Bit ADCIN in Control register 0 selects between the two options. See Figure 7. It’s default value is “ ...

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... Look-Up Tables The X96012 memory array contains two 64-byte look-up tables. One is associated to pin I1’s output current generator and the other to pin I2’s output current generator, through their corresponding D/A converters. The output of each look-up table is the byte contained in the selected row. By default these bytes are the inputs to the D/A converters driving pins I1 and I2 ...

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... Rx. This resistance may be connected externally to pin Rx of the X96012, or may be selected from one of three internal values. Bits I1FSO1 and I1FSO0 select the full scale output current setting for I1 as described in “I1FSO1 - I1FSO0: Current Generator 1 Full Scale Output Set Bits (Non-volatile)” ...

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... STATUS REGISTER FIGURE 10. LOOK-UP TABLE ADDRESSING Power-on Reset When power is applied to the VCC pin of the X96012, the device undergoes a strict sequence of events before the current outputs of the D/A converters are enabled. When the voltage at VCC becomes larger than the power-on reset threshold voltage (V bits from non-volatile memory into volatile registers ...

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... Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions. See Figure 13. On power-up of the X96012, the SDA pin is in the input mode. Serial Start Condition All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH ...

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... SDA OUTPUT FROM RECEIVER START FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER X96012 Memory Map The X96012 contains a 2176 bit array of mixed volatile and nonvolatile memory. This array is split up into four distinct parts, namely: (Refer to Figure 15). • General Purpose Memory (GPM) • Look-up Table 1 (LUT1) • ...

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... ACK. The master then terminates the transfer by generating a STOP condition. At this time, if all data bits are volatile, the X96012 is ready for the next read or write operation. If some bits are nonvolatile, the X96012 begins the internal write cycle to the nonvolatile memory. During the internal nonvolatile write cycle, the X96012 does not respond to any requests from the master ...

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... As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. A Page Write operation cannot be performed on the page at locations 80h through 8Fh. The next section describes the special cases within that page. 19 X96012 WRITE S T ADDRESS SLAVE ...

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... Address Byte, a second START, and a second Slave Address byte with the R/W bit set to “1”. After each of the three bytes, the X96012 responds with an ACK. Then the X96012 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte ...

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... Data Protection There are four levels of data protection designed into the X96012: 1- Any Write to the device first requires setting of the WEL bit in Control 6 register; 2- The Block Lock can prevent Writes to certain regions of memory; 3- The Write Protection pin disables any writing to the X96012; 4- The ...

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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 22 X96012 M14.173 M B ...