u6264b Alliance Memory, Inc, u6264b Datasheet

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u6264b

Manufacturer Part Number
u6264b
Description
Standard 8k X 8 Sram
Manufacturer
Alliance Memory, Inc
Datasheet

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April 20, 2004
Features
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Pin Configuration
DQ0
DQ1
DQ2
8192 x 8 bit static CMOS RAM
70 ns Access Times
Common data inputs and
outputs
Three-state outputs
Typ. operating supply current
Standby current:
< 2 µA at T
Data retention current at 2 V:
< 1 µA at T
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges:
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: PDIP28 (600 mil)
VSS
QS 9000 Quality Standard
A12
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
70 ns: 10 mA
-40 to 85 °C
-40 to 125 °C
11
1
2
3
4
5
6
7
8
9
10
12
13
14
Top View
0 to 70 °C
a
a
PDIP
SOP
SOP28 (330 mil)
≤ 70 °C
≤ 70 °C
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ4
DQ3
Description
The U6264B is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Write
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word read will
be available at the outputs DQ0 -
DQ7. After the address change, the
data outputs go High-Z until the
new read information is available.
The data outputs have no preferred
state. If the memory is driven by
CMOS levels in the active state,
and if there is no change of the
- Standby
- Data Retention
1
Pin Description
Signal Name
A0 - A12
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Signal Description
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
address, data input and control
signals W or G, the operating cur-
rent (at I
value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows
standby requirements by activation
with TTL-levels too.
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150 µA typ.
Standard 8K x 8 SRAM
to
O
= 0 mA) drops to the
achieve
U6264B
low
power

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u6264b Summary of contents

Page 1

... DQ4 VSS 14 15 DQ3 Top View April 20, 2004 Description The U6264B is a static RAM manu- factured using a CMOS process technology with the following ope- rating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge L), or the falling edge ...

Page 2

... U6264B Block Diagram A11 A12 A10 Address Change Detector E2 E1 Truth Table Operating Mode Standby/not selected Internal Read Read Write * Memory Cell Array 256 Rows x 256 Columns Sense Amplifier/ Write Control Logic Clock Generator ...

Page 3

... April 20, 2004 Symbol Min -40 -40 T -55 stg - Symbol Conditions CC(DR U6264B , as well as I Max. Unit 0 0 °C 70 °C 85 125 °C °C 125 150 °C 100 mA Min. Max. Unit 4.5 5 ...

Page 4

... U6264B Electrical Characteristics Supply Current - Operating Mode Supply Current - Standby Mode (CMOS level) Supply Current - Standby Mode (TTL level) Supply Current - Data Retention Mode Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current High Low ...

Page 5

... Data Retention Mode E2-Controlled ≥ CC(DR) t Data Retention DR 0.8 V ≤ 0 E2(DR) : min min t rec cR U6264B Max. Unit rec ...

Page 6

... MHz ° U6264B Access Time ZMD U6264BS2K 07LL C 0425 960 510 Min. Max Leadfree Option blank = Standard Package G1 = Leadfree Green Package Power Consumption blank = Standard (only A-Type) ...

Page 7

... Output G April 20, 2004 , Addresses Valid t a(A) Previous Data Valid t v( Addresses Valid t t a(E) su(A) t t(QX su(A) a(E) t t(QX) t a(G) t t(QX) High Addresses Valid t su(E) t su( su(A) w(W) t su(D) Input Data Valid t dis(W) High-Z 7 Output Data Valid t dis(E) t dis(E) t dis(G) Output Data Valid t h(A) t h(D) t t(QX) U6264B ...

Page 8

... U6264B Write Cycle 2 (E1-controlled Input DQ i Output G Write Cycle 3 (E2-controlled Input DQ i Output G undefined The information describes the type of component and shall not be considered as assured characteristic. Terms of delivery and rights to change design reserved Addresses Valid ...

Page 9

... April 20, 2004 Grenzstraße 28 • D-01109 Dresden • • D-01101 Dresden • Germany Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de Zentrum Mikroelektronik Dresden AG U6264B ...

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