aduc7032 Analog Devices, Inc., aduc7032 Datasheet - Page 113

• Manufacturer Part Number: aduc7032
• Description: Microconverter Integrated, Precision Battery Sensor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
SPI Control Register :
Name :
Address :
Default Value :
Access :
Function :
Bit
15-13
12
11
10
9
8
7
6
5
4
3
2
1
0
Description
Reserved and should be written as zero
Continuous transfer enable
Set by user to enable continuous transfer.
In master mode the transfer will continue until no valid data is available in the TX register. SS will be asserted and remain
asserted for the duration of each 8-bit serial transfer until TX is empty
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in
the SPITX register then a new transfer is initiated after a stall period
Loop back enable
Set by user to connect MISO to MOSI and test software
Cleared by user to be in normal mode
Slave output enable
Set by user to enable the slave output
Cleared by user to disable slave output
Slave select input enable
Set by user in master mode to enable the output
SPIRX overflow overwrite enable
Set by user, the valid data in the RX register is overwritten by the new serial byte received
Cleared by user, the new serial byte received is discarded
SPITX underflow mode
Set by user to transmit the previous data
Cleared by user to transmit 0
Transfer and interrupt mode (master mode)
Set by user to initiate transfer with a write to the SPITX register. Interrupt will occur when TX is empty
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt will occur when RX is full
LSB first transfer enable bit
Set by user the LSB is transmitted first
Cleared by user the MSB is transmitted first
Reserved and should be written as zero
Serial clock polarity mode bit
Set by user, the serial clock idles high
Cleared by user the serial clock idles low
Serial clock phase mode bit
Set by user, the serial clock pulses at the beginning of each serial bit transfer
Cleared by user, the serial clock pulses eat end of each serial bit transfer
Master mode enable bit
Set by user to enable master mode
Cleared by user to enable slave mode
SPI enable bit
Set by user to enable the SPI
Cleared to disable the SPI
SPICON
0xFFFF0A10
0x0000
Read/Write
The 16-bit MMR configures the Serial Peripheral Interface.
Table 79 : SPICON MMR Bit Descriptions
Rev. PrD | Page 113 of 128
ADuC7032