aduc7032 Analog Devices, Inc., aduc7032 Datasheet - Page 62

• Manufacturer Part Number: aduc7032
• Description: Microconverter Integrated, Precision Battery Sensor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
By default the ADCFLT = 0x07 which configures the ADCs for
a through-put of 1.0KHz with all other filtering options (Chop,
Running Average, Averaging Factor and Sinc3 Modify) being
disabled. A typical filter response based on this default
configuration is shown in Figure 19 below.
Figure 19 : Typical Digital Filter Response at FADC=1.0kHz (ADCFLT = 0x0007)
An additional ‘Sinc3 Modify’ bit (ADCFLT[7]) is also available
in the ADCFLT register. This bit is set by user code to modify
the standard Sinc3 frequency response increasing the filter stop-
band rejection by 5dBs approx. This is achieved by inserting a
second notch (NOTCH2) at FNOTCH2 = 1.333 X FNOTCH
where FNOTCH is the location of the 1st notch in the response.
There is a slight increase in ADC noise if this bit is active.
Figure 20 shows the modified 1KHz filter response when the
Sinc3 modify bit is active. The ‘new’ notch is clearly visible at
1.33KHz as is the improvement in stop-band rejection when
compared to the standard 1KHz response above.
Figure 20 : ModifiedSinc3 Digital Filter Response at FADC=1.0kHz (ADCFLT =
0x0087)
In ADC Normal Power Mode, the maximum ADC through-put
rate is 8KHz which is configured by setting the SF and AF bits
in the ADCFLT MMR to 0, with all other filtering options
disabled. This results in 0x0000 written to ADCFLT and a
typical 8KHz filter response based on these settings is shown
below in Figure 21.
[dB]
[dB]
H(f)
H(f)
-100
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
0
0
0
500
500
1000
1000
1500
1500
2000
2000
2500
2500
3000
3000
3500
3500
4000
4000
4500
4500
Rev. PrD | Page 62 of 128
5000
5000
f
f
A modified version of the 8KHz filter response can be
configured by setting the ‘Running Average’ bit (ADCFLT[14]).
This has the effect of introducing an additional running average
by 2 filter on all ADC output samples. This further reduces the
ADC output noise and while maintaining an 8KHz ADC
through-put rate the ADC settling time is increased by 1 full
conversion period. The modified frequency response for this
configuration is shown below in Figure 22.
Figure 22 : Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x4000)
At very low throughput rates, the chop bit in the ADCFLT
register can be enabled to minimize offset errors and more
importantly and temperature drift in the ADC DC errors. With
Chop enabled, there are again 2 primary variables (Sinc3
decimation factor and averaging factor) available to allow the
user select an optimum filter response trading off filter
bandwidth against ADC noise.
For example, with the CHOP bit ADCFLT[15] set to 1,
increasing the SF value (ADCFLT[6:0]) to 0x1F (31dec) and
selecting an AF value (ADCFLT[13:8]) of 0x16 (22dec) results
in an ADC through-put of 10Hz. The frequency response in
this case is shown in Figure 23.
Figure 21 : Typical Digital Filter Response at FADC=8KHz, (ADCFLT = 0x0000)
[dB]
[dB]
H(f)
H(f)
-100
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
0
0
0
2000
2000
4000
4000
6000
6000
8000
8000
10000
10000
12000
12000
14000
14000
16000
16000
18000
18000
ADuC7032
20000
20000
22000
22000
24000
24000
f [Hz]
f [Hz]