lm2502sm National Semiconductor Corporation, lm2502sm Datasheet - Page 12

• Manufacturer Part Number: lm2502sm
• Description: Mobile Pixel Link Mpl Display Interface Serializer And Deserializer
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
WRITE TRANSACTION
The WRITE transaction consists of two MC edges of control
information followed by 8 MC edges of write data. Since
WRITE transactions transfer information on both edges of
MC it takes 5 MC cycles to complete a write transaction. The
MD0 line carries the Start bit (High), the A/D (Address/Data)
READ TRANSACTION
The READ transaction is variable in length. It consists of four
sections.
In the first section the Master sends a READ_Command to
the slave. This command is sent in a single MC cycle (2
edges) and uses a similar format to the 1st cycle of the
WRITE transaction. The MD0 line carries the Start bit (High)
and the A/D (Address/Data) bit. The MD1 line carries the
R/W* bit (High for reads) and the CS1/2 bit.
The third section consists of the transfer of the read data
from the Slave to the Master. Note that the READ_Data
operates on single-edge strobing (Rising Edge ONLY).
Therefore the back channel data signaling rate is
forward channel (Master-to-Slave direction). When the Slave
is ready to transmit data back to the Master it drives the MD
lines High to indicate start of read data, followed by 8 MC
cycles of the actual read data payload. As in the WRITE
command MD0 carries D0–7 and MD1 carries D8–5. The
Master monitors for the start bit transition (Low to High) and
FIGURE 8. Dual MD Link WRITE Transaction
(Continued)
FIGURE 9. READ_Command and TA’
1
⁄
2
of the
12
bit and then the data payload of 8 bits (D0–7). The MD1 line
carries the R/W* bit (Read/Write*), the CS1/2 bit and then
the data payload of 8 bits (D8–15). The data payload is sent
least significant bit (LSB) first. The CS1/2 bit denotes which
Chipset pin was active. CS1/2 = HIGH designates that CS1*
is active (Low). CS1/2 = LOW designates that CS2* is active
(Low). CS1* and CS2* LOW is not allowed.
In the second section (TA’) the MD lines are turned around,
such that the Master becomes the receiver and Slave be-
comes the transmitter. The Slave must drive the MD lines
low by the 14th clock edge. It may then idle the line at the
Logic Low state or drive the line High to indicate that read
data transmission is starting. This ensures that the MD lines
are a stable LOW state and that the Low-to-High transition of
the “Start” bit is seen by the Master.
selects the best strobe to sample the incoming data on. This
is done to account for the round trip delay of the interconnect
and application data rate.
The Master detects the location of the START bit on MD0
and selects the best strobe for data capture. Skew between
the data lines is constrained tighter in the Master-to-Slave
direction (Write) than in the Read direction due to the data
rate difference. The Master uses its internal clock (multiple
phases) to latch the data.
The fourth and final section (TA”) occurs after the read data
has been transferred from the Slave to the Master. In the
20093307
20093308