lm2502sm National Semiconductor Corporation, lm2502sm Datasheet - Page 23

• Manufacturer Part Number: lm2502sm
• Description: Mobile Pixel Link Mpl Display Interface Serializer And Deserializer
• Manufacturer: National Semiconductor Corporation

Application Information
DISPLAY APPLICATION
The LM2502 chipset is intended for Interface between a host
(processor) and a Display. It supports a 16 or 8-bit CPU style
interface and can be configured for i80 or m68 modes.
The Master side connection is shown in Figure 19. Input
Clock frequency and the selection of the PLL_CON setting
are determined by system parameters. These include the
required display bandwidth, the Master load rate and the
Display Driver input timing requirements. See the System
Considerations section for more details.
The Display side parallel bus may be connected to one or
two displays. Each display has its own chipselect signal. If
only one display is required, the unused CS signal should be
tied HIGH (V
open on the Slave. The Slave provides an optional clock
DDIO
) on the Master, and the unused output left
FIGURE 18. LM2502 UFBGA Package PWR (V
(Continued)
23
output. If this is desired the CLKDIS
tied HIGH. A different PLL_CON setting can be used to alter
the frequency if desired. As the Divisor setting in the Slave is
not used for data recovery. For the dual display application,
the multidrop bus should be laid out to minimize any result-
ing stub lengths on the Data, A/D, and control signals.
If required, the Slave output clock can be enabled to provide
a output frequency reference. The frequency can be ad-
justed by setting different PLL_CON (divisor) settings (on the
Slave). This can then be used as a frequency reference
signal to the display module or other subsystem (ie camera
module). If the CLK output is not needed, tie the Slave
CLKDIS
ever the MPL link is enabled.
DD
*
pin Low to disable it. The Clock is available when
) and GND (V
SS
) Balls
20093321
*
pin needs to be also
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