lm25119psqx National Semiconductor Corporation, lm25119psqx Datasheet - Page 19

• Manufacturer Part Number: lm25119psqx
• Description: Lm25119 Wide Input Range Dual Synchronous Buck Controller
• Manufacturer: National Semiconductor Corporation

the spikes on the switch waveform at high load. A snubber
may not be necessary with an optimized layout.
ERROR AMPLIFIER COMPENSATION
R
characteristics to accomplish a stable voltage loop gain. One
advantage of current mode control is the ability to close the
loop with only two feedback components, R
The voltage loop gain is the product of the modulator gain and
the error amplifier gain. For the 3.3V output design example,
the modulator is treated as an ideal voltage-to-current con-
verter. The DC modulator gain of the LM25119 can be mod-
eled as:
Note that A is the gain of the current sense amplifier which is
10 in the LM25119. The dominant low frequency pole of the
modulator is determined by the load resistance (R
output capacitance (C
is:
For R
then f
DC Gain
For the 3.3V design example, the modulator gain vs. frequen-
cy characteristic is shown in
Components R
as a Type II configuration. The DC gain of the amplifier is
80dB with a pole at 0Hz and a zero at f
R
lator pole leaving a single pole response at the crossover
frequency of the voltage loop. A single pole response at the
crossover frequency yields a very stable loop with 90 degrees
of phase margin. For the design example, a conservative tar-
get loop bandwidth (crossover frequency) of 11kHz was se-
lected. The compensation network zero (f
selected at least an order of magnitude less than the target
crossover frequency. This constrains the product of R
and C
x R
COMP
COMP
COMP
LOAD
P(MOD)
COMP
, C
x C
(MOD)
x C
COMP
FIGURE 9. Modulator Gain and Phase
= 3.3V / 8A = 0.413Ω and C
COMP
for a desired compensation network zero 1 / (2
= 532Hz
COMP
= 0.413Ω / (10 x 8mΩ) = 5.16 = 14.2dB
COMP
). The error amplifier zero cancels the modu-
and C
) to be about 1.1kHz. Increasing R
and C
OUT
HF
). The corner frequency of this pole
configure the error amplifier gain
COMP
Figure
configure the error amplifier
9.
OUT
= 724μF (effective)
COMP
ZEA
ZEA
= 1 / (2
) should be
and C
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LOAD
COMP
COMP
) and
COMP
(40)
(41)
π
π
x
.
,
19
while proportionally decreasing C
amp gain. Conversely, decreasing R
increasing C
sign example C
selected as 36.5kΩ. These values configure the compensa-
tion network zero at 640Hz. The error amp gain at frequencies
greater than f
(14.3dB).
The overall voltage loop gain can be predicted as the sum (in
dB) of the modulator gain and the error amp gain.
If a network analyzer is available, the modulator gain can be
measured and the error amplifier gain can be configured for
the desired loop transfer function. If the K factor is between 2
and 3, the stability should be checked with the network ana-
lyzer. If a network analyzer is not available, the error amplifier
compensation components can be designed with the guide-
lines given. Step load transient tests can be performed to
verify acceptable performance. The step load goal is mini-
mum overshoot with a damped response. C
to the compensation network to decrease noise susceptibility
of the error amplifier. The value of C
small since the addition of this capacitor adds a pole in the
FIGURE 11. Overall Voltage Loop Gain and Phase
FIGURE 10. Error Amplifier Gain and Phase
COMP
ZEA
COMP
is: R
, decreases the error amp gain. For the de-
was selected as 6800pF and R
COMP
/ R
FB2
, which is approximately 5.22
COMP
COMP
HF
, increases the error
must be sufficiently
while proportionally
HF
can be added
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30126218
COMP
was