lm25119psqx National Semiconductor Corporation, lm25119psqx Datasheet - Page 3

• Manufacturer Part Number: lm25119psqx
• Description: Lm25119 Wide Input Range Dual Synchronous Buck Controller
• Manufacturer: National Semiconductor Corporation

Pin Descriptions
Pin
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
VCCDIS
COMP1
COMP2
PGND1
RAMP1
AGND
DEMB
Name
CSG1
VCC1
RES
LO1
CS1
SS1
EN2
SS2
FB1
FB2
RT
Description
Bias supply pin. Locally decouple to PGND1 using a low ESR/ESL capacitor located as close to
controller as possible.
Low side MOSFET gate drive output. Connect to the gate of the channel1 low-side synchronous
MOSFET through a short, low inductance path.
Power ground return pin for low side MOSFET gate driver. Connect directly to the low side of the
channel1 current sense resistor.
Kelvin ground connection to the external current sense resistor. Connect directly to the low side of
the channel1 current sense resistor.
Current sense amplifier input. Connect to the high side of the channel1 current sense resistor.
PWM ramp signal. An external resistor and capacitor connected between the SW1 pin, the RAMP1
pin and the AGND pin sets the channel1 PWM ramp slope. Proper selection of component values
produces a RAMP1 signal that emulates the current in the buck inductor.
An external capacitor and an internal 10µA current source set the ramp rate of the channel1 error
amp reference. The SS1 pin is held low when VCC1 or VCC2 < 4V, UVLO < 1.25V or during thermal
shutdown.
Optional input that disables the internal VCC regulators when external biasing is supplied. If VCCDIS
>1.25V, the internal VCC regulators are disabled. The externally supplied bias should be coupled to
the VCC pins through a diode. VCCDIS has a 500kΩ pull-down resistor to ground to enable the VCC
regulators when the pin is left floating. The pull-down resistor can be overridden by pulling VCCDIS
above 1.25V with a resistor divider connected to the external bias supply.
Feedback input and inverting input of the channel1 internal error amplifier. A resistor divider from the
channel1 output to this pin sets the output voltage level. The regulation threshold at the FB1 pin is
0.8V.
Output of the channel1 internal error amplifier. The loop compensation network should be connected
between this pin and the FB1 pin.
If the EN2 pin is low, channel2 will be disabled. Channel1 and all other functions remain active. The
EN2 has a 50kΩ pull-up resistor to enable channel2 when the pin is left floating.
Analog ground. Return for the internal 0.8V voltage reference and analog circuits.
The internal oscillator is set with a single resistor between RT and AGND. The recommended
maximum oscillator frequency is 1.5MHz which corresponds to a maximum switching frequency of
750kHz for either channel. The internal oscillator can be synchronized to an external clock by
coupling a positive pulse into RT through a small coupling capacitor.
The restart timer pin for an external capacitor that configures the hiccup mode current limiting. A
capacitor on the RES pin determines the time the controller will remain off before automatically
restarting in hiccup mode. The two regulator channels operate independently. One channel may
operate in normal mode while the other is in hiccup mode overload protection. The hiccup mode
commences when either channel experiences 256 consecutive PWM cycles with cycle-by-cycle
current limiting. After this occurs, a 10µA current source charges the RES pin capacitor to the 1.25V
threshold which restarts the overloaded channel.
Output of the channel2 internal error amplifier. The loop compensation network should be connected
between this pin and the FB2 pin.
Feedback input and inverting input of the channel2 internal error amplifier. A resistor divider from the
channel2 output to this pin sets the output voltage level. The regulation threshold at the FB2 pin is
0.8V.
Logic input that enables diode emulation when in the low state. In diode emulation mode, the low
side MOSFET is latched off for the remainder of the PWM cycle when the buck inductor current
reverses direction (current flow from output to ground). When DEMB is high, diode emulation is
disabled allowing current to flow in either direction through the low side MOSFET. A 50kΩ pull-down
resistor internal to the LM25119 holds DEMB pin low and enables diode emulation if the pin is left
floating.
An external capacitor and an internal 10µA current source set the ramp rate of the channel2 error
amp reference. The SS2 pin is held low when VCC1 or VCC2 < 4V, UVLO < 1.25V or during thermal
shutdown.
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