pi2eqx5804d Pericom Semiconductor Corporation, pi2eqx5804d Datasheet - Page 10

• Manufacturer Part Number: pi2eqx5804d
• Description: 5.0gbps 4-lane Pcie? 2.0 Redrivertm With Equalization & Emphasis
• Manufacturer: Pericom Semiconductor Corporation

Transferring Data
Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the
most significant bit (MSB) first (see the I
force the master into a wait state.
Note: Byte-write and byte-read transfers have a fixed offset of 0x00, because of the very small number of configuration bytes. An
offset byte presented by a host to the PI2EQX5804D is not used.
Addressing
Up to eight PI2EQX5804D devices can be connected to a single I
indicating either a read or write operation. The address for a specific device is determined by the A0, A1 and A4 input pins.
Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowl-
edge clock pulse, the PI2EQX5804D will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW
during the HIGH period of this clock pulse as indicated in the I
acknowledge after each byte has been received.
Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI2EQX5804D will watch the next
byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the
following clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop
bit. For a write cycle, the first data byte following the address byte is a dummy or fill byte that is not used by the PI2EQX5804D.
This byte is provided to provided compatibility with systems implementing 10-bit addressing. Data is transferred with the most
significant bit (MSB) first. After each block write, address pointer will reset to byte 0.
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A6
1
Address Assignment
A5
1
A4
Program
2
C Data Transfer diagram). The PI2EQX5804D will never hold the clock line SCL LOW to
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis
A3
0
2
2
C Data Transfer diagram. The PI2EQX5804D will generate an
10
C bus. The PI2EQX5804D supports 7-bit addressing, with the LSB
A2
0
10-0170
A1
Programmable
www.pericom.com
A0
PI2EQX5804D
P-0.1
R/W
1=R, 0=W
05/28/10