pi2eqx5804d Pericom Semiconductor Corporation, pi2eqx5804d Datasheet - Page 19

• Manufacturer Part Number: pi2eqx5804d
• Description: 5.0gbps 4-lane Pcie? 2.0 Redrivertm With Equalization & Emphasis
• Manufacturer: Pericom Semiconductor Corporation

Characteristics of the SDA and SCL bus lines for F/S-mode I
Notes:
1. All values referred to V
2. A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the V
the falling edge of SCL.
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Symbol
f
t
t
t
t
t
t
t
t
t
t
C
SCL
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
r
f
SU;STO
BUF
b
SCL clock frequency
Hold time (repeated) START condition. After
this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Buss free time between a STOP and STOP
condition
Capacitive load for each bus line
Parameter
IHmin
and V
ILmax
levels.
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis
Conditions
19
2
C-bus devices
10-0170
0
4.0
4.7
4.0
4.7
5.0
250
–
4.0
4.7
–
Min.
IHmin
(1)
of the SCL signal) to bridge the undefined region of
Typ.
www.pericom.com
Max.
100
–
–
–
–
–
–
1000
300
–
–
400
PI2EQX5804D
P-0.1
kHz
µs
ns
µs
pF
Unit
05/28/10