ncn6001 ON Semiconductor, ncn6001 Datasheet - Page 10

• Manufacturer Part Number: ncn6001
• Description: Compact Smart Card Interface Ic
• Manufacturer: ON Semiconductor

PROGRAMMING
Write Register " WRT_REG
[b5:b7] and five data bits [b0:b4] as depicted in Table 1.
These bits are concatenated into a single byte to accelerate
the programming sequence. The register can be updated
when CS is low only.
9. When operating in Asynchronous mode, [b5:b7] are compared with the external voltage levels present pins C4/S0 and C8/S1 (respectively
10. The CRD_RST pin reflects the content of the MOSI WRT_REG[b4] during the chip programming sequence. Since this bit shall be Low to
Table 1. WRT_REG Bits Definitions
b0
b1
b2
b3
b4
b5,
b6,
b7
The WRT_REG register handles three command bits
pins 15 and 14).
address the internal register of the chip, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
If (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then
Else if (b7 + b6 + b5) = 110 then
Else if (b7 + b6 + b5) = 101 then
End if
If (b7 + b6 + b5) <> 110 and (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 111 then
Else if (b7 + b6 + b5) = 110 then
Else if (b7 + b6 + b5) = 101 then
End if
Drives CRD_RST pin (Note 10)
000
001
010
011
100
110
101
111
Case 00
Case 01
Case 10
Case 11
b1 drives C4
b0 drives C8
Case (b4 + b3 + b2 + b1 + b0) = 0000
Case (b4 + b3 + b2 + b1 + b0) = 0001
Case (b4 + b3 + b2 + b1 + b0) = 0010
Case (b4 + b3 + b2 + b1 + b0) = 0011
Case 00
Case 01
Case 10
Case 11
b3 drives CRD_CLK
b2 drives CRD_IO
Case (b4 + b3 + b2 + b1 + b0) = 0000
Case (b4 + b3 + b2 + b1 + b0) = 0001
Case (b4 + b3 + b2 + b1 + b0) = 0010
Case (b4 + b3 + b2 + b1 + b0) = 0011
CRD_VCC = 0 V
CRD_VCC = 1.8 V
CRD_VCC = 3.0 V
CRD_VCC = 5.0 V
CRD_DET = NO
CRD_DET = NC
SPI_MODE = Special
SPI_MODE = Normal
CRD_CLK = L
CRD_CLK = CLK_IN
CRD_CLK = CLK_IN/2
CRD_CLK = CLK_IN/4
CRD_DET = NO
CRD_DET = NC
SPI_MODE = Special
SPI_MODE = Normal
Select Asynchronous Card #0 (Note 9), four chips bank CS signal
Select Asynchronous Card #1 (Note 9), four chips bank CS signal
Select Asynchronous Card #2 (Note 9), four chips bank CS signal
Select Asynchronous Card #3 (Note 9), four chips bank CS signal
Select External Asynchronous Card, dedicated CS signal
Select External Synchronous Card, dedicated CS signal
Set Card Detection Switch polarity, Set SPI_MODE normal or special. Set CRD_CLK slopes Fast or Slow.
Reserved for future use
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NCN6001
10
WRT_REG[b4] during the chip programming sequence.
Since this bit shall be Low to address the internal register of
the chip, care must be observed as this signal will be
immediately transferred to the CRD_RST pin.
The CRD_RST pin reflects the content of the MOSI