ncn6001 ON Semiconductor, ncn6001 Datasheet - Page 25

• Manufacturer Part Number: ncn6001
• Description: Compact Smart Card Interface Ic
• Manufacturer: ON Semiconductor

SMART CARD CLOCK DIVIDER
threefold:
the microprocessor to get the Duty Cycle window as defined
by the ISO7816−3 specification.
programming functions when CS is Low as depicted in
Figure 25 and Figure 24. The clock input stage (CLK_IN)
can handle a 20 MHz frequency maximum signal, the
divider being capable to provide a 1:4 ratio. Of course, the
ratio must be defined by the engineer to cope with the Smart
Card considered in a given application and, in any case, the
output clock [CRD_CLK] shall be limited to 20 MHz
maximum. In order to minimize the dI/dt and dV/dV
developed in the CRD_CLK line, the output stage includes
a special function to adapt the slope of the clock signal for
different
MOSI register (Table 2: WRT_REG Bits Definitions and
Functions) whatever be the clock division.
ISO7816−3 specification, the divider is synchronized by the
The main purpose of the built−in clock generator is
In addition, the NCN6001 adjusts the signal coming from
The byte content of the SPI port, B2 & B3, fulfills the
In order to avoid any duty cycle out of the smart card
1. Adapts the voltage level shifter to cope with the
2. Provides a frequency division to adapt the Smart
3. Controls the clock state according to the smart
VCC
CLK_IN
SYNC
B2
B0
B1
B3
different voltages that might exist between the
MPU and the Smart Card.
Card operating frequency from the external clock
source.
card specification.
applications.
Programming
This function is programmed by the
CRD_CLK
Division
Figure 25. Basic Clock Divider and Level Shifter
CRD_CLK Slope
Programming
ASYNC
SYNC
http://onsemi.com
B
A
NCN6001
SEL
25
DIGITAL_MUX
OUT
NOTE: Bits [B0...B3] come from SPI data
last flip flop, thus yielding a constant 50% duty cycle,
whatever be the divider ratio (Figure 24). Consequently, the
output CRD_CLK frequency division can be delayed by
four CLK_IN pulses and the microcontroller software must
take this delay into account prior to launch a new data
transaction. On the other hand, the output signal Duty Cycle
cannot be guaranteed 50% if the division ratio is 1 and if the
input Duty Cycle signal is not within the 46–56% range.
automatically routed to the level shifter and control block
according to the mode of operation.
U1
The input signals CLK_IN and MOSI/b3 are
CLOCK_IN
CLOCK : 1
CLOCK : 2
CLOCK : 4
Figure 24. Typical Clock Divider Synchronization
CRD_CLK
B2
B3
LEVEL SHIFTER
AND CONTROL
CLOCK programming is activated
by the B2 + B3 logic state
Clock is updated upon
CLOCK: 4 rising edge
These bits program
CLOCK = 1:1 ratio
CRD_CLK
CRD_VCC
Internal
CLOCK
Divider