pdi1394p11 NXP Semiconductors, pdi1394p11 Datasheet - Page 17

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pdi1394p11

Manufacturer Part Number
pdi1394p11
Description
3-port Physical Layer Interface
Manufacturer
NXP Semiconductors
Datasheet

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Part Number
Manufacturer
Quantity
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Part Number:
pdi1394p11ABD
Manufacturer:
NXP/恩智浦
Quantity:
20 000
SPD = Speed Code
P
X transmitted as 0, ignored on receive.
Philips Semiconductors
23.0 RECEIVE
When data is received by the phy from the serial bus, it will transfer the data to the link for further processing. The phy will assert ‘Receive’ on
the CTL lines and ‘1’ on each D pin. The phy indicates the start of the packet by placing the speed code on the data bus. The phy will then
proceed with the transmittal of the packet to the link on the D lines while still keeping the ‘Receive’ status on the CTL pins. Once the packet has
been completely transferred, the phy will assert ‘Idle’ on the CTL pins which will complete the receive operation.
NOTE: The speed is a phy-link protocol and not included in the CRC.
23.1 RECEIVE TIMING WAVEFORMS
NOTE:
The speed code for the receiver is as follows:
NOTE:
24.0 POWER CLASS BITS IN SELF–ID PACKET
The settings of the PC[0:2] pins appear in the pwr field of the self–ID packet. Bit 21 is transmitted first, followed by bit 22 and then bit 23.
1999 Apr 09
D [0:3]
00XX
0100
0
pwr[21:23]
3-port physical layer interface
å Pn = packet data
000
001
010
100
101
011
110
111
Node may be powered from the bus, and is using up to 1 W. An additional 9 W is needed to enable the LLC and higher layers.
Node does not need power and does not repeat power.
Node is self powered, and provides a minimum of 15 W to the bus.
Node is self powered, and provides a minimum of 30 W to the bus.
Node is self powered, and provides a minimum of 45 W to the bus.
Node may be powered from the bus, and is using up to 1 W.
Node may be powered from the bus, and is using up to 1 W. An additional 2 W is needed to enable the LLC and higher layers.
Node may be powered from the bus, and is using up to 1 W. An additional 5 W is needed to enable the LLC and higher layers.
PHY
CTL [0:1]
PHY
D [0:3]
NOTE:
SPD = Speed Code
P
0
P
n
= Packet Data
DATA RATE
100
200
0000
(Mbit/s)
00
1111
10
Figure 9. Receive Timing Waveforms
1111
10
SPD
10
17
DESCRIPTION
10
P
0
10
P
1
P
10
n
0000
00
0000
00
PDI1394P11
SV00234
Product specification

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