w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 101

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

11. SMART CARD INTERFACE
Because of similarity of transmission protocol to UART, the register map of Smart Card interface of
Winbond I/O is designed to be UART-like for easy programming. Details of these registers are described
as follows.
11.1 Receiver Buffer Register (RBR, read only at "base address + 0" when BDLAB =
0)
Data from IC card are buffered in this register for host to read.
11.2 Transmitter Buffer Register (TBR, write only at "base address + 0" when
BDLAB = 0)
Host writes to this register to send data to IC card.
11.3 Interrupt Control Register (ICR, at "base address + 1" when BDLAB = 0)
This 8-bit register allows the four types of interrupts. The interrupt system can be completely disabled
by resetting bits 0 through 4 of the Interrupt Control Register (ICR). A selected interrupt can be enabled
by setting the appropriate bits of this register to a logical 1.
Bit 7-5: These bits are always logic 0.
Bit 4: ESCPTI. Setting this bit to a logical 1 enables SCPSNT interrupt when a card is inserted.
Bit 3: This bit is always logic 0.
Bit 2: ESSRI. Setting this bit to a logical 1 enables Smart Card interface status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables RBR data ready interrupt.
7
0
6
0
5
0
4
3
0
2
1
0
Enable RBR Data Ready Interrupt (ERDRI)
Enable TBR Empty Interrupt (ETBREI)
Enable SSR Interrupt (ESSRI)
Enabel SCPSNT Interrupt (ESCPTI)
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Publication Release Date: Nov. 2000
PRELIMINARY
W83627SF
Revision 0.60