w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 4

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

3.2 REGISTER DESCRIPTIONS------------------------------------------------------------------------------------------------------------- 36
4. UART PORT--------------------------------------------------------------------------------------------------- 47
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ------------------------------------ 47
4.2 REGISTER ADDRESS -------------------------------------------------------------------------------------------------------------------- 47
5. CIR RECEIVER PORT------------------------------------------------------------------------------------- 57
5.1 CIR REGISTERS---------------------------------------------------------------------------------------------------------------------------- 57
3.1.4 Write Precompensation------------------------------------------------------------------------------------------------------------ 25
3.1.5 Perpendicular Recording Mode ------------------------------------------------------------------------------------------------ 25
3.1.6 FDC Core ----------------------------------------------------------------------------------------------------------------------------- 25
3.1.7 FDC Commands--------------------------------------------------------------------------------------------------------------------- 25
3.2.1 Status Register A (SA Register) (Read base address + 0) --------------------------------------------------------------- 36
3.2.2 Status Register B (SB Register) (Read base address + 1) --------------------------------------------------------------- 38
3.2.3 Digital Output Register (DO Register) (Write base address + 2) ----------------------------------------------------- 40
3.2.4 Tape Drive Register (TD Register) (Read base address + 3) ----------------------------------------------------------- 40
3.2.5 Main Status Register (MS Register) (Read base address + 4) --------------------------------------------------------- 41
3.2.6 Data Rate Register (DR Register) (Write base address + 4)------------------------------------------------------------ 41
3.2.7 FIFO Register (R/W base address + 5)---------------------------------------------------------------------------------------- 43
3.2.8 Digital Input Register (DI Register) (Read base address + 7) --------------------------------------------------------- 45
3.2.9 Configuration Control Register (CC Register) (Write base address + 7) ------------------------------------------ 46
4.2.1 UART Control Register (UCR) (Read/Write)-------------------------------------------------------------------------------- 47
4.2.2 UART Status Register (USR) (Read/Write) ---------------------------------------------------------------------------------- 50
4.2.3 Handshake Control Register (HCR) (Read/Write) ------------------------------------------------------------------------ 51
4.2.4 Handshake Status Register (HSR) (Read/Write)--------------------------------------------------------------------------- 52
4.2.5 UART FIFO Control Register (UFR) (Write only) ------------------------------------------------------------------------- 53
4.2.6 Interrupt Status Register (ISR) (Read only)--------------------------------------------------------------------------------- 54
4.2.7 Interrupt Control Register (ICR) (Read/Write)----------------------------------------------------------------------------- 55
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) -------------------------------------------------------------- 55
4.2.9 User-defined Register (UDR) (Read/Write)---------------------------------------------------------------------------------- 56
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)------------------------------------------------------------------- 57
5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR) ---------------------------------------------------------------------------- 57
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR)------------------------------------------------------------------------------- 57
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) --------------------- 58
5.1.5 Bank0.Reg4 - CIR Control Register (CTR) ---------------------------------------------------------------------------------- 58
5.1.6 Bank0.Reg5 - UART Line Status Register (USR) -------------------------------------------------------------------------- 59
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ------------------------------------------------------------ 60
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Publication Release Date: Nov. 2000
W83627SF
P R E L I M I N A R Y
Revision 0.60