sak-c164ci-l16m3v Infineon Technologies Corporation, sak-c164ci-l16m3v Datasheet - Page 68

• Manufacturer Part Number: sak-c164ci-l16m3v
• Description: 16-bit Single-chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

Preliminary
Demultiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
2)
3)
Data Sheet
RW-delay and
Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
Therefore address changes before the end of RD have no impact on read cycles.
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
t
1)
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
t
t
t
t
68
55
57
A
+
t
CC -16 +
CC 15 +
SR –
C
+
t
F
min.
Max. CPU Clock
(125 ns at 16 MHz CPU clock without waitstates)
= 16 MHz
t
64
F
t
F
max.
11 +
–
–
t
F
min.
–
-16 +
TCL - 16
+
1 / 2TCL = 1 to 16 MHz
Variable CPU Clock
t
F
t
F
C164CI-L16M3V
max.
TCL - 20
+ 2
–
–
t
A
Low Power
V1.0, 2003-01
+
t
F
1)
Unit
ns
ns
ns