sak-cic310-osmx2ht Infineon Technologies Corporation, sak-cic310-osmx2ht Datasheet - Page 7

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sak-cic310-osmx2ht

Manufacturer Part Number
sak-cic310-osmx2ht
Description
Flexray Communication Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
Data Sheet
– Flexible interrupt generation
16-bit External Memory Interface Unit (XMU)
– 16-bit wide data bus (D[15:0])
– Automatic data assembly/disassembly operation
– Data width of external bus master can be 8-bit or 16-bit
– 13-bit wide address bus (A[12:0])
– Address extension mechanism to 32-bit
– Read (RD) and write (WR) Bus control signal
– External synchronous/asynchronous wait state bus control signal (WAIT)
– External master chip select (CSFPI) to access on-chip devices connected to the
High performing on-chip crossbar bus structure
– 32-bit crossbar slave interface for FlexRay
– 32-bit crossbar slave interface for Ports and System Control
– 32-bit crossbar slave interface for MLI communication
– 32-bit crossbar slave interface for MLI and DMA peripheral
– 32-bit crossbar master interface for Host Communication Interfaces
– 32-bit crossbar master interface for DMA
Versatile High-Speed Synchronous Serial Channels (SSC) for Host Communication
– Full-duplex or half-duplex operation
– Automatic half-duplex pad control
– SSC supports proprietary protocol to drive an integrated move engine
– Maximum Master Mode baud rate:
– Maximum Slave Mode baud rate:
Versatile High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication and Host Communication
– Fully transparent read/write access supported (including remote programming)
– Complete address range of target controller available
– Special protocol to transfer data, address offset, or address offset and data
– Error control using a parity bit
– 32-bit, 16-bit, and 8-bit data transfers
– Address offset width: from 1 to 16 bit
– Baud rate:
Full automotive temperature range: -40°C to +125°C
26 digital general purpose I/O lines, 20 digital general purpose input lines
Digital I/O ports with 3.3 V capability
Clock Generation Unit with PLL
Core supply voltage of 1.5 V
I/O voltage of 3.3 V
crossbar switch
Maximum baud rate (master mode) of 40 MBit/s (@ 80 MHz module clock)
Maximum baud rate (slave mode) of 20 MBit/s (@ 80 MHz module clock)
baud rate definition by the corresponding fractional divider
Maximum baud rate of 40 MBit/s (@ 80 MHz module clock)
f
MLI
/ 2 (symmetric shift clock approach),
f
SSC
f
SSC
8
/ 4
/ 2
SAK-CIC310-OSMX2HT
Summary of Features
V 2.2, 2007-06
IFLEX

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