lmh1982sqx National Semiconductor Corporation, lmh1982sqx Datasheet
lmh1982sqx
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lmh1982sqx Summary of contents
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... SDI output jitter specifications. The LMH1982 is offered in a space-saving 32- pin LLP package and provides low total power consumption of about 250 mW (typical). Typical Video Genlock Block Diagram © 2009 National Semiconductor Corporation LMH1982 Features ■ Two simultaneous LVDS output clocks with selectable frequencies and Hi-Z capability: — ...
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... Functional Block Diagram Typical Loop Filter Topology Ordering Information Package Part Number LMH1982SQ 32-Pin LLP LMH1982SQE LMH1982SQX www.national.com Package Marking Transport Media 1k Units Tape and Reel L1982SQ 250 Units Tape and Reel 4.5k Units Tape and Reel 2 30052403 30052439 NSC Drawing SQA32A ...
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Connection Diagram Top View 32-Pin LLP 3 30052402 www.national.com ...
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Pin Descriptions Pin No. Pin Name – 1 VC_FREERUN 2, 10, 18, 22, 26 21, 27, 28 HREF_A 5 VREF_A 6 REF_SEL 7 HREF_B 8 VREF_B C_ENABLE 14 GENLOCK 15 ...
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General Description .............................................................................................................................. 1 Features .............................................................................................................................................. 1 Applications ......................................................................................................................................... 1 Typical Video Genlock Block Diagram ..................................................................................................... 1 Functional Block Diagram ...................................................................................................................... 2 Typical Loop Filter Topology .................................................................................................................. 2 Ordering Information ............................................................................................................................. 2 Connection Diagram ............................................................................................................................. 3 Pin Descriptions ................................................................................................................................... 4 ...
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Genlock And Input Reference Control Registers .................................................................. 26 9.2 Genlock Status And Lock Control Register ......................................................................... 26 9.3 Input Control Register ...................................................................................................... 26 9.4 PLL 1 Divider Register ..................................................................................................... 27 9.5 PLL 4 Charge Pump Current Control Register ..................................................................... ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Machine Model Supply Voltage Supply Voltage Input Voltage ...
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Symbol Parameter I Output Hi-Z Leakage Current OZ t Rise Time R t Fall Time F t TOF Output Delay Time (Note D_TOF 9) Clock Outputs (Pins 19, 20, 23, 24) Jitter 27 MHz TIE Peak-to-Peak SD Output Jitter (Note ...
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Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the electrical tables under conditions different than those tested. Note 5: Typical values represent the most likely ...
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Typical Performance Characteristics Test conditions 3.3V 2.5V, Genlock mode, outputs initialized. H sync and V sync signals to REF_A inputs are from DD VDD the LMH1981 sync separator, which receives an analog video reference signal from ...
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TOF Output Delay Using 27 MHz TOF Clock Note 16: GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1716, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1716, TOF_LPFM = 525, REF_LPFM = 525, TOF_OFFSET = 262; all other ...
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Supported Standards and Timing Formats Table 1 lists the known supported standard timing formats and includes the relevant parameters that can be used to configure the LMH1982 for the input reference and output timing. For the related programming instructions, see ...
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INPUT TIMING PARAMETERS Format PLL 1 PLL 1 Reference Feedback Divider 1 Divider 1 800 1080i/60 [5] [4000] 1080i/59.94 5 4004 1 960 1080i/50 [5] [4800] 48 kHz AES 2 1125 sample clock 1. The PLL 1 reference divider value ...
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For interface control register map and definitions, refer to section 9 INTERFACE CONTROL REGISTER DEFINI- TIONS. 2.1 148.35 MHz PLL Initialization Sequence The following programming sequence is required to initialize PLL 3 and generate ...
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Program the output clock frequency for the desired output format. Refer to section 5.1 Programming The Output Clock Frequencies. 2. Program the output TOF timing for the desired output format. Refer to section 5.2 Programming The Output Format Timing. ...
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I 2 C_RSEL = 0 (register 00h). The reference signals should be 3.3V LVCMOS signals within the input voltage range specified in the Electrical Character- istics ...
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TABLE 5. HD Clock Frequency Selection HD_CLK (MHz) HD_FREQ Register 08h 74.25 0h 74.25/1.001 1h 148.5 2h 148.5/1.001 3h 5.2 Programming The Output Format Timing When PLL 1 is stable and locked to the input reference, the output format timing ...
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FIGURE 3. Functional Block Diagram – TOF Generation and Output Initialization Circuitry www.national.com 18 30052437 ...
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Output TOF Clock The TOF pulse is derived from a counter chain, which re- ceives either output clock (SD_CLK or HD_CLK) from a 2:1 MUX block, as shown in Figure 3. The TOF clock from the MUX can be ...
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REF_LPFM = Reference Format Total Lines per Frame 5.2.4 Input-Output Frame Rate Ratio The input-output frame rate ratio is also used for resetting the internal counters for output initialization. The ratio is the Input Frame Rate / Output Frame Rate, ...
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VCXO, which may be in Free Run or Holdover operation. To disable output alignment to an arbitrary reference frame when the reference is reapplied, set EN_TOF_RST = 0 before the reference returns. After ...
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TABLE 7. Summary of Genlock Status Bits and Flag Outputs Mode Control Bits Conditions GNLK Genlock mode, Reference valid, PLLs locking Genlock mode, Reference valid, PLLs locked Genlock mode, Reference lost, Free Run operation Genlock mode, Reference lost, Holdover operation ...
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Loop Response Optimization Tips The need to support various input reference formats will usu- ally require a diverse range of PLL divider values, which can each yield a different loop response assuming all other PLL parameters are kept the ...
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Read Sequence Read sequences are comprised of two I is the address access transfer, which consists of a write se- quence that transfers only the address to be accessed. The second is the data read transfer, which starts at ...
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INTERFACE CONTROL REGISTER DEFINITIONS TABLE Interface Control Register Map Register Default D7 D6 Address Data 00h A3h GNLK_I 2 C GNLK 01h 86h 02h 00h RSV RSV 03h 01h RSV RSV 04h ...
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Genlock And Input Reference Control Registers Register 00h Bits 2-0: H Input Error Max Count (H_ERROR) The H_ERROR bits control the reference detector's error threshold, which determines the maximum number of missing H sync pulses before indicating a LOR. ...
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MHz input and H sync inputs. Alternatively, it's possible to use an external counter circuit to divide the 27 MHz clock to a lower frequency (e.g. like H sync) input, so ...
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Bits 7-0: TOF Reset (TOF_RST) This register contains the 8 LSBs of TOF_RST. When PLL 1 is phase locked to the reference, both H sync and V sync in- puts are used to reset the frame-based counters used for output ...
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For more information on setting the loop response, see section 7.0 LOOP RESPONSE . To minimize lock time, using a large or maximum I result in faster PLL settling time due to a wider loop band- width. ...
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TYPICAL SYSTEM BLOCK DIAGRAMS FIGURE 9. Analog Reference Genlock for Triple-rate SDI Video FIGURE 10. SDI Reference Genlock for Triple-rate SDI Video www.national.com 30 30052407 30052408 ...
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FIGURE 11. Triple-rate SDI Loop-through FIGURE 12. Combined Genlock or Loop-through for Triple-rate SDI Video 31 30052409 30052410 www.national.com ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 32-Pin LLP NS Package Number SQA32A 32 ...
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Notes 33 www.national.com ...
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