sta538 STMicroelectronics, sta538 Datasheet
sta538
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sta538 Summary of contents
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... W mono into 4 Ω speaker at 3.3 V – 100 mW stereo into 16 Ω headphone, 1.2 W mono into 4 Ω speaker at 3.3 V Order codes Part number STA538B STA538Q January 2007 TM VFQFPN52 Package TFBGA48 (tube) VFQFPN52 (tube) Rev 1 STA538 TFBGA48 1/59 www.st.com 1 ...
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... I C interface disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Volume control and gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.1 6.1.2 6.1.3 6.2 Application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 Configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/59 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 High-pass filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Programmable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 STA538 ...
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... STA538 7 Driver configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 Serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 Serial formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.4.1 8.4.2 8.4.3 8.4 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 Data transition and change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.6 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.6.1 9.6.2 9.7 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.7.1 9.7.2 9.7.3 9.7.4 10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.2 General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11 Package information ...
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... Contents 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4/59 STA538 ...
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... STA538 1 Introduction The STA538 is a digital stereo class-D audio amplifier. It includes an audio DSP proprietary high-efficiency class-D driver and CMOS power output stage intended for high-efficiency digital-to-power-audio conversion for portable applications. The STA538 also provides output capabilities for FFX provides high-quality digital amplification ...
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... This section includes connection diagrams and pin descriptions for the following packages: ● TFBGA48 ● VFQFPN52 2.1 TFBGA48 package 2.1.1 Connection diagram Figure 2 shows the connection diagram for the TFBGA48 package. Figure 2. Package: TFBGA48 6/ STA538 ...
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... STA538 2.1.2 Pin description Table 1. Package: TFBGA48 Pin # Name D7 RST_N D1 XTI E1 MCLK33 G3 SELCLK33 D2 XTO CLKOUT/ C7 PWM2B F1 SCL G1 SDA G2 I2CDIS G8 STBY B7 MUTE H6 BICLKI H5 LRCLKI E2 SDATAI BICLKO/ G6 PWM1A LRCLKO/ G5 PWM1B SDATAO/ G4 PWM2A INL H8 INR G7 VBIAS D8 VCM F8 AVDD E8 AGND Connection diagrams and pin descriptions ...
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... Channel 1 power supply Supply Channel 2 power supply Ground Channel 1 power ground Ground Channel 2 power ground Supply Pre-driver supply Ground Pre-driver ground Supply Digital supply Ground Digital ground Supply I/O ring supply Ground I/O ring ground Parameter Min STA538 Description Typ Max Unit C/W ...
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... STA538 2.2 VFQFPN52 package 2.2.1 Connection diagram Figure 3 shows the connection diagram for the VFQFPN52 package. Figure 3. Package: VFQFPN52 26 14 Connection diagrams and pin descriptions 9/59 ...
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... ADC left channel line input or microphone input Analog ADC right channel line input input/output Analog ADC microphone bias voltage input/output Analog ADC Common mode voltage input/output Supply ADC analog supply Ground ADC analog ground Analog input ADC High reference voltage STA538 Description ...
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... STA538 Table 3. Package: VFQFPN52 (continued) Pin # Name 7 VLO 40 FILT 42 VDDPLL 41 GNDPLL 16 OUT1A 19 OUT1B 25 OUT2A 22 OUT2B POWERFAULT/ 31 EADP 15 VCC1A 20 VCC1B 26 VCC2A 21 VCC2B 17 GND1A 18 GND1B 24 GND2A 23 GND2B 30 VCC33 27 GND33 13 VDD1 12 GND1 44 VDD2 43 GND2 29 VDDIO1 28 GNDIO1 50 VDDIO2 49 GNDIO2 Connection diagrams and pin descriptions Type ...
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... Electrical specifications 3 Electrical specifications This section includes the electrical specifications for the STA538. 3.1 Maximum and recommended operating conditions Table 4 provides the maximum ratings and Table 4. Absolute maximum ratings Signal VDD/VDD1/VDD2 AVDD VDDPLL VCC1A/1B/2A/2B VCC33 VDDIO STG T AMB Note: All grounds must be within 0 ...
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... STA538 3.2 Electrical characteristics Table 6 lists the device’s electrical characteristics (see also Table 6. Electrical characteristics Symbol Parameter Eff Output power efficiency Output stage N/PMOS on- R dson resistance Logic power supply current at IstbyL standby Bridges power supply current in IstbyP standby Logic power supply current at ...
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... P (mW) at 1.8 V 300 195 110 61 Parameter Lock time P (mW (mW (mW (mW) at 3.6 V 860 1000 530 630 300 350 165 195 P (mW (mW) at 3.6 V 1100 1300 677 812 380 450 210 250 Value 200 µs STA538 ...
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... STA538 3.4 ADC performance values Table 11. Programmable gain performance Dynamic range 1 kHz 3.3 V supply Dynamic range 1 kHz 1.8 V supply Dynamic range 1 kHz 3.3 V supply A-weighted Dynamic range 1 kHz 1.8 V supply A-weighted SNDR 1 kHz 3.3 V supply SNDR 1 kHz 1.8 V supply SNDR 1 kHz 3.3 V supply A-weighted SNDR 1 kHz 1.8 V supply A-weighted THD 1 kHz (-1 dB input) 1.8 V supply THD 1 kHz (-1 dB input) 3 ...
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... Digital processing 4 Digital processing The STA538 processor block is a digital block providing two channels of audio processing and channel-mapping capability. 4.1 Signal processing flow stereo ADC data can be selected. The I ADC sampling frequency can be selected from 8 kHz to 48 kHz interface disabled When pin I2CDIS = 1, the SDA, SCL, LRCLKO and BICLKO pins can be pulled high or low to change certain parameters of operation ...
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... STA538 4.3 Volume control and gain The volume control structure of the STA538 consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from + -91.5 dB example, if register LVOL = 0x00 or +36 dB and register MVOL = 0x18 or -12 dB, then the total gain for the left channel is +24 dB ...
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... IDF Buffer INFOUT REFOUT STRB STRB_ BYPASS FRAC_CTRL DITHER_DISABLE FRAC_INPUT 18/59 INFIN FBCLK INFIN Phase frequency pump and divider (PFD) FBCLK Loop frequency divider Fractional controller NDIV LOCKP Lock detect FILT LF Charge VCONT loop filter VCO FVCO Output frequency divider STA538 PHI ...
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... The PLL output PHI is generated by dividing the FVCO by the output division factor (ODF). The divider that divides the FVCO to generate the clock to the core is called the output frequency divider. In the STA538, the ODF is fixed to be divisible by 2 and cannot be configured. Lock-detect circuit ...
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... C1 = 250 pF, and pF. Figure 5. PLL filter scheme Table 10 on page 14 5.2 Configuration examples The STA538 PLL can be configured in two ways: ● default startup configuration ● direct PLL programming The default startup configuration reads the device’s defaults. With this configuration not necessary to program the PLL dividers directly as some presets are used ...
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... STA538 If register bit PLLCFG0.FRAC_CTRL = 0, then VCO INFIN PHI VCO In the above equations: FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0] IDF = Input division factor (refer to previous formulas) LDF = Loop division factor (refer to previous formulas) ODF = Output division factor = INFIN frequency ...
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... IDF should be equal to 4 otherwise LDF become less than 8 (FRAC_CTRL must be 1): LDF = floor(49.152/(19.2/IDF FRACT = round([(49.152/(19.2/IDF))-floor(49.152/(19.2/IDF))]*2 Using the above configuration, the system clock is 49.151953125 MHz, the approximate static error (that is, 1 ppm). 22/59 STA538 27602 15728 ...
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... This section describes the analog-to-digital converter (ADC). 6.1 Functional description The STA538 analog input is provided through a low power, low voltage, stereo audio analog- to-digital converter front-end designed for audio applications. It includes a programmable gain amplifier, anti-aliasing filter, low-noise microphone biasing circuit, a third-order MASH2-1 delta-sigma modulator, digital decimating filter, and a first-order DC-removal filter ...
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... INR AVDD C5 C1 AGND VHI C6 C2 VLO VCM C7 C3 VBIAS C8 C4 STA538 Unit Hz Hz degree dB for details). C1, C2, C3 (These capacitors must be placed very close to their respective pins) C5, C6 µF (Low ESR and ESL capacitors are recommended) VSSA plane must be ...
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... STA538 6.3 Configuration examples The ADC sampling frequency can be selected from three values: ● normal (from 32 kHz to 48 kHz) ● low (from 16 kHz to 24 kHz) ● very-low (from 8 kHz to 12 kHz) The setting is done through register bits MISC.ADC_FS_RANGE (see details). For all other settings, register ADCCFG is used (see details) ...
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... PWM1B (external bridge PWM command for output 1B) PWM2A (external bridge PWM command for output 2A) PWM2B (external bridge PWM command for output 2B) EADP (external audio power-down signal) PWMINT1 and PWMINT2 on page PWMINT1 and PWMINT2 on page STA538 Table 17. 52 input signal straight to the 52). ...
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... STA538 8 Serial audio interface This section includes information about the audio interface. 8.1 Specifications The serial-to-parallel interface and the parallel-to-serial interface can have different sampling rates. The following terms are used in this section: ● BICLK active edge: Pins SDATAI, SDATAO, LRCLKI, LRCLKO always change synchronously with BITCLK active edges ...
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... SDATAI propagation delay from BICLKI/O active edge Sdatao setup time to BICLKI/O strobing edge Sdatao hold time from BICLKI/O strobing edge 28/ DST DHT Parameter DDA Symbol Min Typ Max DDA t 10 DST t 10 DHT STA538 Unit ...
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... STA538 8.3 Slave mode In this mode, pins BICLKI/O and pins LRCLKI/O are configured as inputs. Figure 8. Slave mode BICLKI/ BICLKO LRCLKI/ LRCLKO SDATAO SDATAI Table 19. Slave mode BICLK cycle time BICLK pulse width high BICLK pulse width low LRCLKI/LRCLKO setup time to BICLK strobing edge ...
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... Data length can be customized for 8-, 16-, 24-, and 32-bit. Figure 9. Right justified LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO Figure 10. Left justified LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI SDATAO 30/ STA538 ...
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... STA538 8.4.1 DSP Figure 11. DSP LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 2 8.4 Figure 12 LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO Left Serial audio interface Right 31/59 ...
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... Figure 13. PCM/IF (non delayed mode) LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI SDATAO 8.4.4 PCM/IF (delayed mode) ● MSB first ● 16-bit data Figure 14. PCM/IF (delayed mode) LRCLKI/ LRCLKO BICLKI/ BICLKO SDATAI/ SDATAO 32/59 Any width STA538 ...
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... In the STA538, the I The 8th bit (LSB) identifies read or write operation (R/W), this bit is set read mode and 0 in write mode. After a start condition, the STA538 identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time ...
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... STA538 again responds with an acknowledgement. The master then initiates another start condition and sends the device select code with the R/W bit set to 1. The STA538 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a stop condition. ...
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... Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA538. The master acknowledges each data byte read and then generates a stop condition terminating the transfer. 2 Figure 15. I ...
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... Reserved Reserved Reserved Bit 3 Bit 2 Bit 1 TIM_SOFT_VOL[3:0] PWM_SHIFT[1:0] MASTER_ DATA_FORMAT[2:0] MAP_L[1:0] MAP_R[1:0] MASTER_ DATA_FORMAT[2:0] MAP_L[1:0] MAP_R[1:0] IDF[3:0] NDIV[5:0] RESET_FA PFE1B PFE2A PFE2B BYPASS_ STBY CLKENBL CALIB P2P_IN_ ADC_FS_RANGE[1:0] ADC CLKENBL INVALID_ MUTE_ BINSS_FBK INP_FBK INT_FBK STA538 Bit 0 MODE MODE ULT CORE_ ...
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... STA538 Table 20. Register summary (continued) Address Name Bit 7 0x29 BISTST0 0x2A BISTST1 0x2B BISTST2 0x2D PWMINT1 0x2E PWMINT2 POWER 0x32 POWST DOWN 10.2 General registers FFXCFG0 Bit 7 Bit 6 MUTE POW_STBY SOFT_VOL_ON Address: 0x00 Type: R/W Buffer: No Reset: 0x75 Description: 7 MUTE: 0: default 1: FFX output is zero ...
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... Bit 7 Bit 6 Address: 0x02 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 SET_VOL_MASTER[7:0]: master volume control: From -127 0.5 dB steps 38/59 Configuration register 1 Bit 5 Bit 4 Bit 3 PWM_MODE[1:0] PWM_SHIFT[1: Master volume control register Bit 5 Bit 4 Bit 3 SET_VOL_MASTER[7:0] STA538 Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 ...
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... STA538 LVOL Bit 7 Bit 6 Address: 0x03 Type: R/W Buffer: No Reset: 0x48 Description: 7:0 SET_VOL_LEFT[7:0]: left channel volume control: 0100 1000: default Left channel volume control (from + -91 0.5 dB steps) Default value corresponds RVOL Bit 7 Bit 6 Address: 0x04 Type: R/W Buffer: No Reset: 0x48 ...
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... LSBs of TIM_TS_FAULT[7:0]: time in which power is held in tri-state mode after a fault signal: Time is TIM_TS_FAULT * 83.33 µs. Default value corresponds to 166.66 µs tri-state time after fault 40/59 Tri-state time-after-fault register 0 Bit 5 Bit 4 Bit 3 TIM_TS_FAULT[15:8] 40. Tri-state time-after-fault register 1 Bit 5 Bit 4 Bit 3 TIM_TS_FAULT(7:0) STA538 Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 ...
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... STA538 TTP0 Bit 7 Bit 6 Address: 0x07 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 MSBs of TIM_TS_POWUP[15:8]: See register TTP1. TTP1 Bit 7 Bit 6 Address: 0x08 Type: R/W Buffer: No Reset: 0x02 Description: 7:0 LSBs of TIM_TS_POWUP[7:0]: time in which power is held in tri-state mode after a power- up signal: Time is TIM_TS_POWUP * 83.33 µs Default value corresponds to 166.66 µs tri-state time after power-up ...
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... Justified 2 001 (default) 010: right justified 100: PCM no delay 101: PCM delay 111: DSP 001: default 0 MASTER_MODE: 0: default 1: serial interface is in master mode 42/59 Serial-to-parallel audio interface configuration register 0 Bit 5 Bit 4 Bit 3 MSB_FIRST Bit 2 Bit 1 MASTER_ DATA_FORMAT[2:0] STA538 Bit 0 MODE ...
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... STA538 S2PCFG1 Bit 7 Bit 6 PDATA_LENGTH[1:0] Address: 0x0B Type: R/W Buffer: No Reset: 0x91 Description: 7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: default Length is (N+ bit Default is 24 bit 5:4 BICLK_OS[1:0]: bit clock oversampling: 01: default Value is (N+ (where fs = sampling frequency) Default 3:2 MAP_L[1:0]: left data-mapping slot: ...
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... I S (default) 010: right justified 100: PCM no delay 101: PCM delay 111: DSP 0 MASTER_ MODE: selects serial interface master/slave mode: 0: slave 1: master (default) 44/59 Parallel-to-serial audio interface configuration register 0 Bit 5 Bit 4 Bit 3 MSB_FIRST Bit 2 Bit 1 MASTER_ DATA_FORMAT[2:0] STA538 Bit 0 MODE ...
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... STA538 P2SCFG1 Bit 7 Bit 6 PDATA_LENGTH[1:0] Address: 0x0D Type: R/W Buffer: No Reset: 0x91 Description: 7:6 PDATA_LENGTH[1:0]: serial-to-parallel interface data length: 10: default Length is (PDATA_LENGTH+ bit Default is 24 bits 5:4 BICLK_OS[1:0]: bit clock oversampling: 01: default Value is (BICLK_OS+ Default 3:2 MAP_L[1:0]: left data-mapping slot: 00: default Value is nth slot ...
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... Type: R/W Buffer: No Reset: 0x00 Description: 7:0 FRAC_INPUT[15:8]: 16 bits are used to set the fractional part of PLL multiplication factor: 0000 0000: default 46/59 PLL configuration register 0 Bit 5 Bit 4 Bit 3 DITHER_DISABLE[1:0] PLL configuration register 1 Bit 5 Bit 4 Bit 3 FRAC_INPUT[15:8] STA538 Bit 2 Bit 1 Bit 0 IDF[3:0] Bit 2 Bit 1 Bit 0 ...
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... STA538 PLLCFG2 Bit 7 Bit 6 Address: 0x16 Type: R/W Buffer: No Reset: 0x00 Description: 7:0 FRAC_INPUT[7:0]: 16 bits are used to set the fractional part of PLL multiplication factor: 0000 0000: default PLLCFG3 Bit 7 Bit 6 STRB STRB_BYPASS Address: 0x17 Type: R/W Buffer: No Reset: 0x00 Description: 7 STRB: asynchronous strobe input to the fractional controller: ...
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... POP-free resistances are connected to output 1B 2 PFE2A: 0: default 1: POP-free resistances are connected to output 2A 1 PFE2B: 0: default 1: POP-free resistances are connected to output 2B 0 RESET_FAULT: 0: default 1: fault signal in the i2c register POWST is reset 48/59 PLL/POP-free configuration register Bit 5 Bit 4 Bit 3 PFE1A PFE1B STA538 Bit 2 Bit 1 Bit 0 PFE2A PFE2B RESET_FAULT ...
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... STA538 PLLST Bit 7 Bit 6 PLL_PWD_ PLL_BYP_ PLL_UNLOCK STATE STATE Address: 0x19 Type: RO Buffer: No Reset: Undefined Description: 7 PLL_UNLOCK: PLL unlock state: 0: PLL is not in unlock state 1: PLL is in unlock state 6 PLL_PWD_ STATE: PLL power-down state: 0: PLL is not in power-down state 1: PLL is in power-down state ...
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... CLKOUT_DIS: CLKOUT PAD disabled 0: default 1: enabled 6:5 CLKOUT_SEL[1:0]: 00: default The CLKOUT output frequency is the PLL output frequency divided by 2 4:0 Reserved 50/59 ADC configuration register Bit 5 Bit 4 Bit 3 INSEL STBY Clock-out configuration register Bit 5 Bit 4 Bit 3 STA538 Bit 2 Bit 1 Bit 0 BYPASS_CALIB CLKENBL Bit 2 Bit 1 Bit 0 CLKOUT_SEL . ...
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... STA538 MISC Bit 7 Bit 6 OSC_DIS P2P_FS_RANGE[2:0] Address: 0x20 Type: R/W Buffer: No Reset: 0x21 Description: 7 OSC_DIS: enable/disable crystal oscillator: 0: default 1: disabled 6:4 P2P_FS_RANGE[2:0]: FFX audio frequency range: 000: very low ( kHz) (default) 001: low ( kHz) (default) 010: normal ( kHz) ...
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... Bit 4 Bit 3 PWM driver configuration register 1 Bit 5 Bit 4 Bit 3 PWM_INT1[7:0] Section 7: Driver configuration on page PWM driver configuration register 2 Bit 5 Bit 4 Bit 3 PWM_INT1[7:0] Section 7: Driver configuration on page STA538 Bit 2 Bit 1 Bit 0 INVALID_INP_ MUTE_INT_FBK FBK Bit 2 Bit 1 Bit 0 26: Bit 2 Bit 1 Bit 0 26: ...
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... STA538 POWST Bit 7 Bit 6 POW_ POW_ POW_FAULT1A POWERDOWN TRISTATE Address: 0x32 Type: RO Buffer: No Reset: Undefined Description: 7 POW_POWERDOWN: power-down bridge: 0: not in power-down state 1: power-down state 6 POW_TRISTATE: 1: power bridge is in tri-state 5 POW_FAULT1A: 1: power bridge fault state 4 POW_FAULT1B: 1: power bridge fault state ...
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... JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ECOPACK specifications are available at: www.st.com. 11.1 Package TFBGA48 Figure 17. Mechanical data (TFBGA48) 54/59 STA538 ® ...
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... STA538 Table 21 gives the package dimensions. Table 21. Package dimensions (TFBGA48) Reference ddd eee fff Databook mm Min Typical 0.15 0.785 0.20 0.25 0.30 4.85 5.00 3.50 4.85 5.00 3.50 0.50 0.75 Package information Max 1.20 0.60 0.35 5.15 5.15 0.08 0.15 0.05 55/59 ...
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... Package information 11.2 Package VFQFPN52 Figure 18. Mechanical data (VFQFPN52 56/59 ) STA538 ...
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... STA538 Table 22 gives the package dimensions. Table 22. Package dimensions (VFQFPN52) Reference ddd Databook mm Min Typical 0.800 0.900 0.020 0.650 0.250 0.180 0.230 7.875 8.000 2.750 5.700 7.875 8.000 2.750 5.700 0.450 0.500 0.350 0.550 Package information Max 1 ...
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... Revision history 12 Revision history Table 23. Document revision history Date 25-Jan-2007 58/59 Revision 1 Initial release STA538 Changes ...
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... STA538 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...