sta538 STMicroelectronics, sta538 Datasheet - Page 20

• Manufacturer Part Number: sta538
• Description: 2 X 1.3 W Class-d Amplifier With Analog Or Digital Input 2.0 Multichannel Digital Audio Processor With Ffx
• Manufacturer: STMicroelectronics

PLL
5.2
20/59
Configuration examples
PLL filter
Figure 5
C1 = 250 pF, and C2 = 82 pF.
Figure 5.
Table 10 on page 14
The STA538 PLL can be configured in two ways:
●
●
The default startup configuration reads the device’s defaults. With this configuration, it is not
necessary to program the PLL dividers directly as some presets are used. In this mode, the
oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256.
The direct PLL programming bypasses the automatic presets allowing direct programming
of the PLL dividers.
The output PLL frequency can be determined as following:
Output division factor:
Relation between input and output clock frequency:
If register bit PLLCFG0.FRAC_CTRL = 1
When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1/2
multiplication. This is recommended in order to keep register bit
PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output
clock spectrum.
default startup configuration
direct PLL programming
ODF = 2
F
F
F
INFIN
VCO
PHI
shows the PLL filter scheme. Recommended values are R1 = 12.5 kΩ ,
= F
= F
= F
PLL filter scheme
VCO
INFIN
XTI
/ ODF
/ IDF
* (LDF + FRACT/2
gives a typical lock time value for the PLL.
C1
R1
16
Ground
+ 1/2
Vc
17
)
C2
17
factor is not in the
STA538