sta538 STMicroelectronics, sta538 Datasheet - Page 21

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sta538

Manufacturer Part Number
sta538
Description
2 X 1.3 W Class-d Amplifier With Analog Or Digital Input 2.0 Multichannel Digital Audio Processor With Ffx
Manufacturer
STMicroelectronics
Datasheet
STA538
If register bit PLLCFG0.FRAC_CTRL = 0, then:
In the above equations:
When selecting the value of IDF, LDF and FRACT make sure the following limits are
maintained:
There are also some additional constraints on IDF and LDF. IDF should be greater than 0,
LDF should be greater than 5 if FRAC_CTRL = 0 and greater than 8 if FRAC_CTRL = 1.
When automatic settings are not used, the PLL must be configured to generate an internal
frequency of N * Fs, where Fs is the LRCLKI pin frequency. Values of N are given in
Table
Table 14.
F
F
FRACT = Decimal equivalent of register bit PLLCFG1.FRAC_INPUT[15:0]
IDF = Input division factor (refer to previous formulas)
LDF = Loop division factor (refer to previous formulas)
ODF = Output division factor = 2
F
F
F
F
2.048 MHz < F
2.048 MHz < F
65.536 MHz < F
14.
VCO
PHI
INFIN
XTI
VCO
PHI
= XTI frequency
= F
= Frequency of the PLL output clock
= F
= VCO frequency
Fs (kHz)
= INFIN frequency
11.025
22.05
176.4
Oversampling table
VCO
44.1
88.2
128
192
INFIN
12
16
24
32
48
64
96
8
/ ODF
* LDF
XTI
INFIN
VCO
< 49.152 MHz
< 16.384 MHz
< 98.304 MHz
4096
4096
4096
2048
2048
2048
1024
1024
1024
512
512
512
256
256
256
N
F
PHI
45.1584
45.1584
45.1584
45.1584
45.1584
32.768
49.152
32.768
49.152
32.768
49.152
32.768
49.152
32.768
49.152
(MHz)
21/59
PLL

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