tda6403a NXP Semiconductors, tda6403a Datasheet - Page 11

• Manufacturer Part Number: tda6403a
• Description: 5 V Mixers/oscillators And Synthesizers For Cable Tv And Vcr 2-band Tuners
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 11 A to D converter levels (note 1)
Note
1. Accuracy is 0.03
P
Table 12 Default bits at power-on reset
The power-on detection threshold voltage V
V
device is reset to the power-on state.
At power-on state, the charge pump current is set to
280 A, the tuning voltage output is disabled, the test bits
T2, T1 and T0 are set to ‘001’ (automatic charge pump
switch ‘ON’) and RSB is set to logic 1.
PUHF is ‘OFF’, which means that the UHF oscillator and
the UHF mixer are switched off. Consequently, the VHF
oscillator and the VHF mixer are switched on. PVHFL and
PVHFH are ‘OFF’, which means that the VHF tank circuit
is working in the VHF I sub-band. The tuning amplifier is
switched off until the first transmission. In that case, the
tank circuit in VHF I is supplied with the maximum tuning
voltage. The oscillator is therefore working at the end of
the VHF I sub-band.
3-wire bus mode (SW = OPEN or V
During a HIGH-level on the CE input (enable line), the data
is clocked into the data register at the HIGH-to-LOW
transition of the clock. The first four bits control the PNP
ports and are loaded into the internal band switch register
on the 5th rising edge of the clock pulse. The frequency
2000 Jan 24
Address byte
Divider byte 1
Divider byte 2
Control byte
Band switch byte
OWER
CC
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
= 2 V at room temperature. Below this threshold, the
NAME
-
A2
ON RESET
1
0
0
0
0
BYTE
ADB
DB1
DB2
CB
BB
V
CC
A1
0
1
1
0
0
.
MSB
X
X
1
0
1
CC
)
POR
A0
0
1
0
1
0
X
X
X
1
1
is set to
0.60
0.45
0.30
0.15
0 to 0.15
X
X
X
0
0
11
bits are loaded into the frequency register at the
HIGH-to-LOW transition of the chip enable line when an
18-bit or 19-bit data word is transmitted (see Figs 4 and 5).
When a 27-bit data word is transmitted, the frequency bits
are loaded into the frequency register on the 20th rising
edge of the clock pulse and the control bits at the
HIGH-to-LOW transition of the chip enable line (see Fig.6).
In this mode, the reference divider is given by the RSA and
RSB bits (see Table 8). The test bits T2, T1 and T0, the
charge pump bit CP, the ratio select bit RSB and the OS
bit can only be selected or changed with a 27-bit
transmission. They remain programmed if an 18-bit or
19-bit transmission occurs. Only RSA is controlled by the
transmission length when the 18-bit or 19-bit format is
used. When an 18-bit data word is transmitted, the most
significant bit of the divider N14 is internally set to logic 0
and the RSA bit is set to logic 1. When a 19-bit data word
is transmitted, the RSA bit is set to logic 0.
A data word of less than 18 bits will not affect the
frequency register of the device. The definition of the bits
is unchanged compared to I
It is not allowed to address the devices with words whose
length is different from 18, 19 or 27 bits.
V
V
V
V
CC
CC
CC
CC
V
to 1.00
to 0.60
to 0.45
to 0.30
VOLTAGE APPLIED ON ADC INPUT
X
X
X
0
0
CC
BITS
V
V
V
V
CC
CC
CC
CC
X
X
0
1
0
TDA6402; TDA6402A;
TDA6403; TDA6403A
MA1
2
C-bus mode.
X
X
X
0
Product specification
MA0
X
X
1
0
LSB
X
X
X
1
0