tda6403a NXP Semiconductors, tda6403a Datasheet - Page 7

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tda6403a

Manufacturer Part Number
tda6403a
Description
5 V Mixers/oscillators And Synthesizers For Cable Tv And Vcr 2-band Tuners
Manufacturer
NXP Semiconductors
Datasheet

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PLL FUNCTIONAL DESCRIPTION
The device is controlled via the I
depending on the voltage applied on the SW input.
A HIGH-level on the SW input enables the 3-wire bus;
CE/AS, DA and CL inputs are used as enable (CE), data
Table 2 Bus mode selection
2000 Jan 24
handbook, halfpage
SW
CE/AS
DA
CL
LOCK/ADC
SYMBOL
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Fig.2
UHFIN2
RFGND
UHFIN1
PVHFH
PVHFL
VHFIN
CE/AS
IFFIL1
IFFIL2
PUHF
FMST
Pin configuration for TDA6402 and
TDA6402A.
SW
DA
TDA6402A
CL
TDA6402;
10
11
12
13
14
4
6
7
8
9
1
2
3
5
11
12
13
14
15
TDA6402A
TDA6402
PIN
MGE690
2
C-bus or the 3-wire bus,
TDA6403A
TDA6403;
19
18
17
16
15
28
27
26
25
24
23
22
21
20
18
17
16
15
14
UHFOSCIB2
UHFOSCOC2
UHFOSCOC1
UHFOSCIB1
VHFOSCOC
OSCGND
VHFOSCIB
GND
IFOUT
V CC
XTAL
VT
CP
LOCK/ADC
HIGH-level or OPEN
enable input
data input
clock input
LOCK/TEST output
3-WIRE BUS MODE
7
and clock inputs respectively. A LOW-level on SW input
enables the I
used as address selection (AS), SDA and SCL input
respectively (see Table 2).
handbook, halfpage
Fig.3
UHFOSCOC2
UHFOSCOC1
UHFOSCIB2
UHFOSCIB1
VHFOSCOC
VHFOSCIB
LOCK/ADC
OSCGND
2
C-bus; the CE/AS, DA and CL inputs are
IFOUT
XTAL
Pin configuration for TDA6403 and
TDA6403A.
GND
V CC
CP
VT
10
11
12
13
14
1
2
3
4
5
6
7
8
9
TDA6402; TDA6402A;
TDA6403; TDA6403A
LOW-level or GND
address selection input
serial data input
serial clock input
ADC input/TEST output
TDA6403A
TDA6403
MGE691
I
2
C-BUS MODE
19
18
17
16
15
28
27
26
25
24
23
22
21
20
Product specification
UHFIN1
UHFIN2
VHFIN
RFGND
IFFIL1
IFFIL2
PVHFL
PVHFH
PUHF
FMST
SW
CE/AS
DA
CL

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