pnx8526 NXP Semiconductors, pnx8526 Datasheet - Page 6

• Manufacturer Part Number: pnx8526
• Description: Programmable Source Decoder With Integrated Peripherals
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 15101
Product data sheet
Table 2:
# indicates multiplexed signal, see
Symbol
PCI_GNT_B
IDSEL
PCI_INTA
PCI_IRDY
PCI_PAR
PCI_PERR
PCI_REQ
PCI_REQ_A
PCI_REQ_B
RESET_IN
PCI_SERR
PCI_STOP
PCI_TRDY
Peripheral Controller Interface (PCI)
Pin
AA4
AF3
V4
AE6
AF8
AD7
Y2
AA2
AA3
W3
AC7
AE7
AD6
Rev. 02 — 11 July 2005
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
Programmable source decoder with integrated peripherials
Section 6.2.1
Description
auxiliary arbitration grant PCI_GNT_B is asserted
to indicate bus access has been granted to an
external PCI master; used where internal arbiter is
configured
initialization device select provides chip select
during configuration read and write transactions
interrupt a is asserted to request an interrupt; this
pin may be configured as an input if the internal
pic is used, or as an output if the external interrupt
controller is used; polarity in active low
initiator ready is asserted during writes to indicate
valid data on AD[31:0]. also asserted during reads
to indicate the target is prepared to accept data.
wait states are inserted until PCI_IRDY and
PCI_TRDY are both asserted
parity supports even parity across the PCI
address/data bus PCI_AD[31:0]) and command/
byte enable bus (PCI_CBE[3:0]); the bus master
drives PCI_PAR for address and write data
phases. the target drives PCI_PAR for the read
data phases
parity error indicates data parity errors during all
PCI transactions except special cycle
arbitration request on PCI bus; request is an
output when using an external arbiter and an input
when using an internal arbiter
auxiliary arbitration PCI_REQ_A on PCI bus; used
in modes where internal arbiter is configured
auxiliary arbitration PCI_REQ_B on PCI bus; used
in modes where internal arbiter is configured
PCI bus global reset
system error
stop is asserted to indicate a request from the
target for the master to stop the current
transmission
target ready is asserted during reads to indicate
valid data on AD[31:0]; it is asserted during writes
to indicate the target is prepared to accept data;
wait states are inserted until PCI_IRDY and
PCI_TRDY are both asserted
for more details.
…continued
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
PNX8526
Alternate
function
#
#
#
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