74aup1g79 NXP Semiconductors, 74aup1g79 Datasheet

no-image

74aup1g79

Manufacturer Part Number
74aup1g79
Description
Low-power D-type Flip-flop; Positive-edge Trigger
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74aup1g79GM
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
74aup1g79GM,115
Manufacturer:
NXP Semiconductors
Quantity:
4 000
Part Number:
74aup1g79GV
Manufacturer:
ON
Quantity:
9 524
Part Number:
74aup1g79GV,125
Manufacturer:
TI
Quantity:
6 958
Part Number:
74aup1g79GWЈ¬125
Manufacturer:
NXP
Quantity:
3 000
1. General description
2. Features
The 74AUP1G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial Power-down applications using I
The I
the device when it is powered down.
The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information
on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D input must be stable one setup time prior to the LOW-to-HIGH clock
transition for predictable operation.
I
I
I
I
I
I
I
I
I
I
I
CC
74AUP1G79
Low-power D-type flip-flop; positive-edge trigger
Rev. 02 — 17 October 2006
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
N
N
N
N
N
N
N
N
range from 0.8 V to 3.6 V.
OFF
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
HBM JESD22-A114-D Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101-C exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
range from 0.8 V to 3.6 V.
CC
= 0.9 A (maximum)
CC
Product data sheet
OFF
.

Related parts for 74aup1g79

74aup1g79 Summary of contents

Page 1

... OFF the device when it is powered down. The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation ...

Page 2

... Temperature range Name 74AUP1G79GW +125 C 74AUP1G79GM +125 C 74AUP1G79GF +125 C 4. Marking Table 2. Marking Type number 74AUP1G79GW 74AUP1G79GM 74AUP1G79GF 5. Functional diagram mna440 Fig 1. Logic symbol 74AUP1G79_2 Product data sheet Low-power D-type flip-flop; positive-edge trigger Description TSSOP5 plastic thin shrink small outline package ...

Page 3

... CP 3 ground ( data output Q 5 not connected 6 supply voltage Rev. 02 — 17 October 2006 74AUP1G79 mna442 74AUP1G79 GND 3 4 001aaf179 Transparent top view Fig 6. Pin configuration SOT891 (XSON6) © NXP B.V. 2006. All rights reserved ...

Page 4

... Active mode and Power-down mode +125 C amb derates linearly with 4.0 mW/K. tot derates linearly with 2.4 mW/K. tot Conditions Active mode Power-down mode 0 3 Rev. 02 — 17 October 2006 74AUP1G79 Output Min Max Unit 0.5 +4 [1] 0.5 +4 ...

Page 5

... GND 0 3 per pin GND GND Rev. 02 — 17 October 2006 74AUP1G79 Min Typ Max 0 ...

Page 6

... GND 0 3 per pin 0 3 Rev. 02 — 17 October 2006 74AUP1G79 Min Typ Max 0.9 V 0.1 - ...

Page 7

... GND 0 3 per pin 0 3 GND. CC Rev. 02 — 17 October 2006 74AUP1G79 Min Typ Max 0 ...

Page 8

... C [1] Min Typ [2] Figure 7 - 19.7 2.6 5.5 2.0 3.8 1.7 3.1 1.4 2.3 1.2 2 203 - 347 - 435 - 550 - 619 [2] Figure 7 - 23.1 3.1 6.3 2.5 4.4 2.1 3.6 1.8 2.8 1.7 2 192 - 324 - 421 - 486 - 550 Rev. 02 — 17 October 2006 74AUP1G79 +125 C Max Min Max Min (85 C) (85 C) (125 11.0 2.4 12.9 2.4 7.0 1.8 8.1 1.8 5.4 1.5 6.4 1.5 4.0 1.1 4.7 1.1 3.4 0.9 4.0 0 170 - 170 - 310 - 300 - 400 - 390 - 490 - 480 - 550 - 510 ...

Page 9

... C [1] Min Typ [2] Figure 7 - 26.6 3.5 7.1 2.8 5.0 2.4 4.1 2.2 3.2 2.0 2 181 - 301 - 407 - 422 - 481 [2] Figure 7 - 36.8 4.7 9.3 3.8 6.4 3.3 5.3 3.0 4.3 2.8 3 128 - 206 - 262 - 269 - 309 Rev. 02 — 17 October 2006 74AUP1G79 +125 C Max Min Max Min (85 C) (85 C) (125 13.6 3.2 15.6 3.2 9.2 2.5 10.7 2.5 7.1 2.2 8.5 2.2 5.4 1.9 6.3 1.9 4.5 1.6 5.0 1 120 - 120 - 190 - 160 - 240 - 190 - 300 - 270 - 320 - 300 ...

Page 10

... 74AUP1G79_2 Product data sheet Low-power D-type flip-flop; positive-edge trigger …continued Figure [1] Min Typ - 3.4 - 0.8 - 0.5 - 0.5 - 0.4 - 0.4 Figure 8 - 3.0 - 0.9 - 0.6 - 0.5 - 0.5 - 0.7 Figure 8 - -1.9 - -0.6 - -0.4 - -0.4 - -0.4 - -0.3 - 5.6 - 2.4 - 1.3 - 0.9 - 0.7 - 0.6 Rev. 02 — 17 October 2006 74AUP1G79 +125 C Max Min Max Min (85 C) (85 C) (125 1.6 - 1.4 - 1.0 - 1.0 - 0.9 - 0.9 - 0.7 - 0.7 - 0 1.4 - 1.4 - 1.0 - 1.0 - 0.9 - 0.9 - 0.8 - 0.8 - 1 ...

Page 11

... where GND GND t PHL Table 9. Rev. 02 — 17 October 2006 74AUP1G79 +125 C Max Min Max Min (85 C) (85 C) (125 ...

Page 12

... Low-power D-type flip-flop; positive-edge trigger GND 1/f max GND PHL Table 9. Input 0 Rev. 02 — 17 October 2006 74AUP1G79 PLH mna647 3 © NXP B.V. 2006. All rights reserved ...

Page 13

... Low-power D-type flip-flop; positive-edge trigger PULSE DUT GENERATOR [ open = for measuring propagation delays, setup and hold times and pulse width R L Rev. 02 — 17 October 2006 74AUP1G79 V EXT 001aac521 of the pulse generator. o EXT , PLH PHL ...

Page 14

... 1 scale (1) ( 0.30 0.25 2.25 1.35 0.65 0.15 0.08 1.85 1.15 REFERENCES JEDEC JEITA MO-203 SC-88A Rev. 02 — 17 October 2006 74AUP1G79 Low-power D-type flip-flop; positive-edge trigger detail 2.25 0.46 1.3 0.425 0.3 0.1 2.0 0.21 ...

Page 15

... Low-power D-type flip-flop; positive-edge trigger scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA MO-252 Rev. 02 — 17 October 2006 74AUP1G79 4 ( EUROPEAN PROJECTION SOT886 ISSUE DATE 04-07-15 04-07-22 © NXP B.V. 2006. All rights reserved ...

Page 16

... Product data sheet Low-power D-type flip-flop; positive-edge trigger scale 1.05 0.35 0.40 0.55 0.35 0.95 0.27 0.32 REFERENCES JEDEC JEITA Rev. 02 — 17 October 2006 74AUP1G79 SOT891 2 mm EUROPEAN ISSUE DATE PROJECTION 05-03-11 05-04-06 © NXP B.V. 2006. All rights reserved ...

Page 17

... The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • ESD HBM and C • Added type number 74AUP1G79GF (XSON6/SOT891) package. 74AUP1G79_1 20050912 74AUP1G79_2 Product data sheet Low-power D-type flip-flop; positive-edge trigger Data sheet status ...

Page 18

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 17 October 2006 74AUP1G79 © NXP B.V. 2006. All rights reserved ...

Page 19

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 17 October 2006 Document identifier: 74AUP1G79_2 ...

Related keywords