74aup2g00 NXP Semiconductors, 74aup2g00 Datasheet - Page 2

no-image

74aup2g00

Manufacturer Part Number
74aup2g00
Description
Low-power Dual 2-input Nand Gate
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
3. Ordering information
Table 1.
4. Marking
Table 2.
5. Functional diagram
6. Pinning information
74AUP2G00_2
Product data sheet
Type number
74AUP2G00DC
74AUP2G00GT
74AUP2G00GM
Type number
74AUP2G00DC
74AUP2G00GT
74AUP2G00GM
Fig 1. Logic symbol
Fig 4. Pin configuration SOT765-1 (VSSOP8)
1
2
5
6
Ordering information
Marking
1A
1B
2A
2B
6.1 Pinning
Package
Temperature range Name
mna712
40 C to +125 C
40 C to +125 C
40 C to +125 C
1Y
2Y
7
3
Fig 2. IEC logic symbol
VSSOP8
XSON8
XQFN8
GND
1A
1B
2Y
Rev. 02 — 15 May 2007
1
2
3
4
1
2
5
6
74AUP2G00
Description
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1
plastic extremely thin quad flat package; no leads; 8
terminals; body 1.6
&
&
mna713
Marking code
p00
p00
p00
001aae362
7
3
8
7
6
5
V
1Y
2B
2A
CC
1.95
1.6
Low-power dual 2-input NAND gate
0.5 mm
Fig 3. Logic diagram (one gate)
0.5 mm
B
A
74AUP2G00
© NXP B.V. 2007. All rights reserved.
Version
SOT765-1
SOT833-1
SOT902-1
mna099
2 of 16
Y

Related parts for 74aup2g00