24lc21a Microchip Technology Inc., 24lc21a Datasheet - Page 3

• Manufacturer Part Number: 24lc21a
• Description: 1k 2.5v Dual Mode I2c Serial Eeprom
• Manufacturer: Microchip Technology Inc.

TABLE 1-2:
 2003 Microchip Technology Inc.
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
Output fall time from V
minimum to V
Input filter spike suppres-
sion (SDA and SCL pins)
Write cycle time
Transmit-Only Mode Parameters
Output valid from VCLK
VCLK high time
VCLK low time
VCLK setup time
VCLK hold time
Mode transition time
Transmit-only power-up
time
Input filter spike suppres-
sion (VCLK pin)
Endurance
Note 1:
2:
3:
4:
Parameter
Not 100% tested. C
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
spike suppression. This eliminates the need for a T
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site.
IL
maximum
AC CHARACTERISTICS
IH
SP
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
—
Symbol
SU
SU
SU
AA
OF
SP
WR
SPVL
SPV
CLK
HIGH
LOW
R
F
HD
HD
BUF
VAA
VHIGH
VLOW
VHST
VHZ
VPU
and V
B
:
:
:
= Total capacitance of one bus line in pF.
:
:
STA
DAT
STO
STA
DAT
HYS
Standard Mode
specifications are due to Schmitt Trigger inputs which provide noise and
Vcc= 2.5-5.5V
4000
4700
4000
4700
4000
4700
4000
4700
4000
Min
250
1M
—
—
—
—
—
—
—
—
—
—
0
0
0
1000
3500
2000
1000
Max
100
300
250
100
—
—
—
—
—
—
—
—
50
10
—
—
—
—
—
—
20 + 0.1
Vcc= 4.5 - 5.5V
1300
1300
1300
Min
600
600
600
100
600
600
600
1M
C
Fast Mode
—
—
—
—
—
—
—
—
—
I
0
0
0
B
specification for standard operation.
1000
Max
400
300
300
900
250
500
100
—
—
—
—
—
—
—
—
50
10
—
—
—
—
—
—
cycles
Units
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
Start condition
(Note 2)
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
(Note 3)
Byte or Page mode
25°C, Vcc = 5.0V, Block
mode (Note 4)
24LC21A
Remarks
B
DS21160F-page 3
100 pF