24lc21a Microchip Technology Inc., 24lc21a Datasheet - Page 8

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24lc21a

Manufacturer Part Number
24lc21a
Description
1k 2.5v Dual Mode I2c Serial Eeprom
Manufacturer
Microchip Technology Inc.
Datasheet

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24LC21A
FIGURE 3-5:
FIGURE 3-6:
3.1.6
After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LC21A.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LC21A
(Figure 3-7).
The 24LC21A monitors the bus for its corresponding
slave
Acknowledge bit if the slave address was true and it is
not in a programming mode.
DS21160F-page 8
Operation
SCL
SDA
SDA
IN
SDA
OUT
SCL
Read
Write
T
SU
address
:
T
STA
SLAVE ADDRESS
SU
:
STA
T
continuously.
SP
Slave Address
BUS TIMING START/STOP
BUS TIMING DATA
T
START
AA
1010000
1010000
T
F
T
HD
T
:
T
It
STA
LOW
HD
:
STA
generates
T
T
HIGH
HD
R/W
1
0
:
DAT
an
T
AA
FIGURE 3-7:
V
HYS
T
1
SU
START
:
DAT
0
T
SU
T
SU
:
SLAVE ADDRESS
STO
:
STO
1
CONTROL BYTE
ALLOCATION
 2003 Microchip Technology Inc.
0
T
R
STOP
0
READ/WRITE
T
BUF
0
R/W
0
A

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