24lcs21 Microchip Technology Inc., 24lcs21 Datasheet - Page 5

• Manufacturer Part Number: 24lcs21
• Description: 1k 2.5v Dual Mode I 2 C? Serial Eeprom
• Manufacturer: Microchip Technology Inc.

3.0
The 24LCS21 can be switched into the Bidirectional
mode (Figure 3-1) by applying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the V
that a logic high level is required to enable write capa-
bility. This mode supports a two-wire bidirectional data
transmission protocol (I
that sends data on the bus is defined to be the transmit-
ter and a device that receives data from the bus is
defined to be the receiver. The bus must be controlled
by a master device that generates the Bidirectional
mode clock (SCL), controls access to the bus and gen-
erates the Start and Stop conditions, while the
24LCS21 acts as the slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
In this mode, the 24LCS21 only responds to
commands for device ‘1010 000X’.
FIGURE 3-1:
FIGURE 3-2:
© 2005 Microchip Technology Inc.
SCL
SDA
V
SDA
(A)
BIDIRECTIONAL MODE
SCL
CLK
CLK
input is disregarded, with the exception
Condition
Start
(B)
MODE TRANSITION
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
2
C
™
Transmit-Only mode
). In this protocol, a device
Acknowledge
Address or
Valid
T
(D)
VHZ
Bidirectional mode
to Change
Allowed
Data
3.1
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 3-2).
3.1.1
Both data and clock lines remain high.
3.1.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
is not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Bidirectional Mode Bus
Characteristics
BUS NOT BUSY (A)
START DATA TRANSFER (B)
STOP DATA TRANSFER (C)
(D)
24LCS21
DS21127F-page 5
Condition
Stop
(C)
(A)