24lcs21 Microchip Technology Inc., 24lcs21 Datasheet - Page 8

• Manufacturer Part Number: 24lcs21
• Description: 1k 2.5v Dual Mode I 2 C? Serial Eeprom
• Manufacturer: Microchip Technology Inc.

24LCS21
4.0
4.1
Following the Start signal from the master, the slave
address (4 bits), three zero bits (000) and the R/W bit,
which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24LCS21.
FIGURE 4-1:
FIGURE 4-2:
DS21127F-page 8
WRITE OPERATION
Byte Write
V
SDA
IN
SCL
CLK
SDA Line
Bus Activity
Bus Activity
Activity
V
BYTE WRITE
VCLK WRITE ENABLE TIMING
CLK
T
VHST
S
A
R
S
T
T
Control
T
Byte
HD
:
STA
A
C
K
After receiving another Acknowledge signal from the
24LCS21, the master device will transmit the data word
to be written into the addressed memory location. The
24LCS21 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle, and during this time the 24LCS21 will not
generate Acknowledge signals (Figure 4-1).
It is required that V
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the V
during the self-timed program operation. Changing
V
operation will not halt programming of the device.
Address
CLK
Word
T
SU
from high-to-low during the self-timed program
:
STO
A
C
K
CLK
Data
© 2005 Microchip Technology Inc.
T
be held at a logic high level
SPVL
C
A
K
S
T
O
P
P
CLK
is ignored