at24c256c ATMEL Corporation, at24c256c Datasheet - Page 6

no-image

at24c256c

Manufacturer Part Number
at24c256c
Description
Two-wire Serial Eeprom
Manufacturer
ATMEL Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
at24c256c-MAHL-T
Manufacturer:
TI/NSC
Quantity:
201
Part Number:
at24c256c-PUL
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
at24c256c-SSHL
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
at24c256c-SSHL-B
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
at24c256c-SSHL-T
Manufacturer:
ATMEL
Quantity:
7 206
Part Number:
at24c256c-SSHL-T
Manufacturer:
ATMEL72
Quantity:
1 600
Part Number:
at24c256c-SSHL-T
Manufacturer:
ATMEL
Quantity:
12 000
Part Number:
at24c256c-SSHL-T
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
at24c256c-SSHL-T
Quantity:
4 760
Company:
Part Number:
at24c256c-SSHL-T
Quantity:
29
Part Number:
at24c256c-XHL-B
Manufacturer:
ATMEL
Quantity:
504
Company:
Part Number:
at24c256c-XHL-B
Quantity:
80
Part Number:
at24c256c-XHL-T
Manufacturer:
MICROCHIP
Quantity:
5 509
Part Number:
at24c256c-XHL-T
Manufacturer:
ATMEL原装
Quantity:
20 000
Company:
Part Number:
at24c256c-XHL-T
Quantity:
5 000
Company:
Part Number:
at24c256c-XHL-T
Quantity:
15 000
3.
6
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (refer to Figure 2). Data changes during SCL high periods will indicate a
start or stop condition as defined below.
Figure 2.
SDA
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other
command (refer to Figure 3).
Figure 3.
SDA
SCL
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (refer to Figure 3).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The AT24C256C features a low-power standby mode that is enabled upon power-up and after the
receipt of the stop bit and the completion of any internal operations.
AT24C256C [Preliminary]
SCL
Start and Stop Definition
S
Data Validity
T
A
R
T
DATA STABLE
CHANGE
DATA
DATA STABLE
S
T
O
P
8568A–SEEPR–11/08

Related parts for at24c256c