at25df161 ATMEL Corporation, at25df161 Datasheet - Page 13

• Manufacturer Part Number: at25df161
• Description: 16-megabit 2.7-volt Minimum Spi Serial Flash Memory
• Manufacturer: ATMEL Corporation

Figure 8-1.
Figure 8-2.
8.2
3687B–DFLASH–11/08
SCK
SO
CS
Dual-Input Byte/Page Program
SI
Byte Program
Page Program
SCK
SO
CS
SI
MSB
HIGH-IMPEDANCE
0
0
0
1
The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program
command and can be used to program anywhere from a single byte of data up to 256 bytes of
data into previously erased memory locations. Unlike the standard Byte/Page Program com-
mand, however, the Dual-Input Byte/Page Program command allows two bits of data to be
clocked into the device on every clock cycle rather than just one.
Before the Dual-Input Byte/Page Program command can be started, the Write Enable command
must have been previously issued to the device (see
Enable Latch (WEL) bit of the Status Register to a logical “1” state. To perform a Dual-Input
Byte/Page Program command, an opcode of A2h must be clocked into the device followed by
the three address bytes denoting the first byte location of the memory array to begin program-
ming at. After the address bytes have been clocked in, data can then be clocked into the device
two bits at a time on both the SOI and SI pins.
The data is always input with the MSB of a byte first, and the MSB is always input on the SOI
pin. During the first clock cycle, bit 7 of the first data byte would be input on the SOI pin while bit
6 of the same data byte would be input on the SI pin. During the next clock cycle, bits 5 and 4 of
the first data byte would be input on the SOI and SI pins, respectively. The sequence would con-
tinue with each byte of data being input after every four clock cycles. Like the standard
Byte/Page Program command, all data clocked into the device is stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page
boundary (A7-A0 are not all 0), then special circumstances regarding which memory locations to
0
2
OPCODE
0
HIGH-IMPEDANCE
MSB
3
0
0
0
4
0
1
0
5
0
2
OPCODE
1
6
0
3
0
7
0
MSB
4
A
ADDRESS BITS A23-A0
8
0
5
A
9
1
6
A
0
7
MSB
A
8
A
A
29 30
9
ADDRESS BITS A23-A0
A
A
10 11
A
A
31 32
MSB
A
D
12
A
D
33
DATA IN BYTE 1
D
34
D
35
A
29 30
D
36
A
AT25DF161 [Preliminary]
D
37 38
A
31 32
D
MSB
D
“Write Enable” on page
D
39
D
33
D
34
DATA IN
D
35
MSB
D
D
36
D
DATA IN BYTE n
D
37 38
D
D
D
D
39
D
D
D
21) to set the Write
D
13