at88sc018 ATMEL Corporation, at88sc018 Datasheet - Page 8

• Manufacturer Part Number: at88sc018
• Description: Cryptocompanion? Chip For Cryptomemory And Cryptorf
• Manufacturer: ATMEL Corporation

1.4.6. Byte Order
1.5.
1.5.1. Memory Locking
8
Table 8.
The system must poll this register (using TWI reads) after sending a command to the chip before attempting to read the
result.
This register cannot be written, attempts to do so will result in a NACK.
The AT88SC018 uses a big-endian byte order for all large integers (addresses, counters) which means that the most
significant byte appears first on the bus. Within this document, that byte is shown on the left side of the page. Arrays
(F values, cryptograms, passwords, digests) appear in index order, byte 0 first (or on the left of the page).
The two wire protocol specifies that the most significant bit within a byte appears first on the bus, and it appears on the
left side of the page.
Memory Architecture
The 4K bit (512 byte) EEPROM within the AT88SC018 is organized into a number of sections, each of which have
different access restrictions.
On shipment from Atmel, certain locations are preloaded by Atmel, per
unknown. The system manufacturer should load all areas important for proper system operation with the desired initial
values.
When this initialization is complete the Lock command should be executed which limits access to the memory per the
restrictions listed later in this section. The system can determine the current lock value by using the
ReadManufacturingID command to read out the ManufacturingID value (MfrID) and the lock byte.
The table below describes the encoding of the least significant two bits of the Lock byte. On shipment from Atmel,
Lock[1:0] will have a value of either 10 or 00, depending on the part number ordered. An AT88SC018 in either of these
two states is considered ‘unlocked’. It is not possible to change from one of these unlocked states to the other.
After the Lock command has been executed, the Lock byte will have the value 0xFF. Subsequent changes to the Lock
byte are impossible.
CryptoCompanion Chip
OK
RstLocked
BadCmd
TimeDelay
AuthFail
―
⎯
⎯
Name
Error Codes
Value
0
1
2
3
4
5
6
7
Enabled, no error.
The AT88SC018 is disabled until the next power cycle or reset assertion. Whenever the
error bits are in this state, the Busy bit in the status register will also be asserted.
The formatting of the command was invalid, or one of the operands had an unacceptable
value.
The AT88SC018 is disabled up for a certain period of time and will respond to
commands after this delay has elapsed. This delay may be a Power Delay
(Section
state, the Busy bit in the status register will also be asserted.
Either authentication must be completed prior to the execution of this command or there
was a problem during the execution of the auth commands themselves.
1.6.2) or Security Delay
(Section
Description
1.6.3). Whenever the error bits are in this
Section
1.5.13. All other data locations are
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