at49lw040 ATMEL Corporation, at49lw040 Datasheet - Page 3
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at49lw040
Manufacturer Part Number
at49lw040
Description
At49lw040 4-megabit Firmware Hub Flash Memory
Manufacturer
ATMEL Corporation
Datasheet
1.AT49LW040.pdf
(29 pages)
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Pin Description
Table 1. Pin Description
3342A–FLASH–6/03
Symbol
IC
RST
INIT
CLK
FWH[3:0]
FWH4
ID[3:0]
Type
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
FWH
Table 1 details the usage of each of the device pins. Most of the pins have dual function-
ality, with functions in both the Firmware Hub and A/A Mux interfaces. A/A Mux
functionality for pins is shown in bold in the description box for that pin. All pins are
designed to be compliant with voltage of V
X
X
X
X
X
X
X
Interface
A/A Mux
X
X
Name and Function
INTERFACE CONFIGURATION PIN: This pin determines which interface
is operational. This pin is held high to enable the A/A Mux interface. This
pin is held low to enable the FWH interface. This pin must be set at power-
up or before return from reset and not changed during device operation.
This pin is pulled down with an internal resistor, with value between 20
and 100 k . With IC high (A/A Mux mode), this pin will exhibit a leakage
current of approximately 200 µA. This pin may be floated, which will select
FWH mode.
INTERFACE RESET: Valid for both A/A Mux and FWH interface
operations. When driven low, RST inhibits write operations to provide data
protection during power transitions, resets internal automation, and tri-
states pins FWH [3:0] (in FWH interface mode). RST high enables normal
operation. When exiting from reset, the device defaults to read array
mode.
PROCESSOR RESET: This is a second reset pin for in-system use. This
pin is internally combined with the RST pin. If this pin or RST is driven low,
identical operation is exhibited. This signal is designed to be connected to
the chipset INIT signal (Max voltage depends on the processor. Do not
use 3.3V.)
A/A Mux = OE
33 MHz CLOCK for FWH INTERFACE: This input is the same as the PCI
clock and adheres to the PCI specification.
A/A Mux = R/C
FWH I/Os: I/O Communication.
A/A Mux = I/O[3:0]
FWH INPUT: Input Communication.
A/A Mux = WE
IDENTIFICATION INPUTS: These four pins are part of the mechanism
that allows multiple parts to be attached to the same bus. The strapping of
these pins is used to identify the component. The boot device must have
ID[3:0] = 0000 and it is recommended that all subsequent devices should
use a sequential up-count strapping (i.e., 0001, 0010, 0011, etc.). These
pins are pulled down with internal resistors, with values between 20 and
100 k when in FWH mode. Any ID pins that are pulled high will exhibit a
leakage current of approximately 200 µA. Any pins intended to be low may
be left to float. In a single FWH system, all may be left floating.
A/A Mux = A[3:0]
CC
+ 0.3V max, unless otherwise noted.
AT49LW040
3