is42s16160a1-7t Integrated Silicon Solution, Inc., is42s16160a1-7t Datasheet - Page 21

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is42s16160a1-7t

Manufacturer Part Number
is42s16160a1-7t
Description
256 Mb Synchronous Dram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
IS42S83200A1
IS42S16160A1
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
10/28/05
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to
WRITE interval is minimum 1 CLK.
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"don't care".
A0-9,11-12
Command
A0-9,11-12
Command
BA0-1
CLK
A10
DQ
BA0-1
CLK
A10
DQ
ACT
Xa
Xa
00
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
Write
Da0
Ya
00
0
Da1
Write
Write interrupted by Read (CL=2, BL=4)
Da0
Ya
00
Write interrupted by Write (BL=4)
0
Da2
Da1
Write
Db0
don't care
Yb
00
0
READ
Yb
00
0
Write
Dc0
Yc
10
0
Dc1
Qb0
Dc2
Qb1
Dc3
Qb2
Qb3
ISSI
21
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