m34d64-w STMicroelectronics, m34d64-w Datasheet - Page 13

• Manufacturer Part Number: m34d64-w
• Description: 64 Kbit Serial I2c Bus Eeprom With Hardware Write Control On Top Quarter Of Memory
• Manufacturer: STMicroelectronics

M34D64
3.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the Device Select Code,
shown in
The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Up to eight memory devices can be connected on a single I
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is
received on Serial Data (SDA), the device only responds if the Chip Enable Address is the
same as the value on the Chip Enable (E0, E1, E2) inputs.
The 8
If a match occurs on the Device Select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
the Device Select code, it deselects itself from the bus, and goes into Standby mode.
Table 5.
1. X = V
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
th
IH
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
Mode
Table 2.: Device select code
or V
Operating modes
IL
.
RW bit
0
1
1
0
0
1
WC
(on Serial Data (SDA), most significant bit first).
V
V
X
X
X
X
IL
IL
(1)
Bytes
32
1
1
1
1
th
bit time. If the device does not match
Start, Device Select, RW = 1
Start, Device Select, RW = 0, Address
reStart, Device Select, RW = 1
Similar to Current or Random Address
Read
Start, Device Select, RW = 0
Start, Device Select, RW = 0
2
C bus. Each one is given a
Initial sequence
Device operation
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