m24256-br STMicroelectronics, m24256-br Datasheet - Page 13

• Manufacturer Part Number: m24256-br
• Description: 512 Kbit And 256 Kbit Serial I2c Bus Eeprom With Three Chip Enable Lines
• Manufacturer: STMicroelectronics

M24512-W, M24512-R, M24512-HR, M24256-BW, M24256-BR
3.5
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Up to eight memory devices can be connected on a single I
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8
If a match occurs on the Device Select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9
the Device Select code, it deselects itself from the bus, and goes into Standby mode.
Table 5.
1. X = V
Current Address
Read
Random Address
Read
Sequential Read
Byte Write
Page Write
Table 2.
th
Mode
IH
bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
or V
(on Serial Data (SDA), most significant bit first).
Operating modes
IL
.
RW bit
1
0
1
1
0
0
WC
V
V
X
X
X
X
IL
IL
(1)
Kbit devices
Kbit devices
128 for 512
64 for 256
Bytes
1
1
1
1
th
Start, Device Select, RW = 1
Start, Device Select, RW = 0, Address
re-Start, Device Select, RW = 1
Similar to Current or Random Address
Read
Start, Device Select, RW = 0
Start, Device Select, RW = 0
bit time. If the device does not match
2
C bus. Each one is given a
Initial sequence
Device operation
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