m24256-br STMicroelectronics, m24256-br Datasheet - Page 6

• Manufacturer Part Number: m24256-br
• Description: 512 Kbit And 256 Kbit Serial I2c Bus Eeprom With Three Chip Enable Lines
• Manufacturer: STMicroelectronics

Description
1
6/35
Description
The M24512-W, M24512-R, M24256-BW and M24256-BR devices are I
electrically erasable programmable memories (EEPROM). They are organized as 64 Kb × 8
bits and 32 Kb × 8 bits, respectively.
I
devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I
bus definition.
The device behaves as a slave in the I
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) (as described in
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages.
ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.
Table 1.
2
E0, E1, E2
SDA
SCL
WC
V
V
C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
CC
SS
Signal name
Logic diagram
Signal names
Table
E0-E2
M24512-W, M24512-R, M24512-HR, M24256-BW, M24256-BR
SCL
WC
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
2), terminated by an acknowledge bit.
3
2
C protocol, with all memory operations synchronized
V CC
M24256-BW
M24256-BR
M24512-W
V SS
M24512-R
Function
SDA
AI02275c
Input
Inputs
I/O
Input
2
C-compatible
Direction
th
bit
2
C