m24256-br STMicroelectronics, m24256-br Datasheet - Page 15

• Manufacturer Part Number: m24256-br
• Description: 512 Kbit And 256 Kbit Serial I2c Bus Eeprom With Three Chip Enable Lines
• Manufacturer: STMicroelectronics

M24512-W, M24512-R, M24512-HR, M24256-BW, M24256-BR
3.6
3.7
3.8
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.
Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write
instruction with Write Control (WC) driven High (during a period of time from the Start
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in
Each data byte in the memory has a 16-bit (two byte wide) address. The most significant
byte
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.
After the Stop condition, the delay t
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
Byte Write
After the Device Select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in
Page Write
The Page Write mode allows up to 64 bytes (for the M24256-BW and M24256-BR) or 128
bytes (for the M24512-W and M24512-R) to be written in a single Write cycle, provided that
they are all located in the same ’row’ in the memory: that is, the most significant memory
address bits (b15-b6 for the M24256-BW and M24256-BR, and b15-b7 for the M24512-W
and M24512-R) are the same. If more bytes are sent than will fit up to the end of the row, a
condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become
overwritten in an implementation dependent way.
The bus master sends from 1 to 64 bytes (for the M24256-BW and M24256-BR) or from 1 to
128 bytes (for the M24512-W and M24512-R) of data, each of which is acknowledged by the
device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (the 7 least significant
address bits only) is incremented. The transfer is terminated by the bus master generating a
Stop condition.
(Table
3.) is sent first, followed by the least significant byte
W
, and the successful completion of a Write operation,
Figure 8.
Figure
(Table
Figure
4.). Bits b15 to b0
8., and waits for two
7..
Device operation
15/35
th