m28w320ect STMicroelectronics, m28w320ect Datasheet - Page 12

• Manufacturer Part Number: m28w320ect
• Description: 32 Mbit 2mb X16, Boot Block 3v Supply Flash Memory
• Manufacturer: STMicroelectronics

M28W320ECT, M28W320ECB
If the second bus cycle is not Write Erase Confirm
(D0h), Status Register bits b4 and b5 are set and
the command aborts.
Erase aborts if Reset turns to V
cannot be guaranteed when the Erase operation is
aborted, the block must be erased again.
During Erase operations the memory will accept
the Read Status Register command and the Pro-
gram/Erase Suspend command, all other com-
mands will be ignored. Typical Erase times are
given in Table 8, Program, Erase Times and Pro-
gram/Erase Endurance Cycles.
See Appendix C, Figure 21, Erase Flowchart and
Pseudo Code, for a suggested flowchart for using
the Erase command.
Program Command
The memory array can be programmed word-by-
word. Two bus write cycles are required to issue
the Program Command.
During Program operations the memory will ac-
cept the Read Status Register command and the
Program/Erase Suspend command. Typical Pro-
gram times are given in Table 8, Program, Erase
Times and Program/Erase Endurance Cycles.
Programming aborts if Reset goes to V
integrity cannot be guaranteed when the program
operation is aborted, the block containing the
memory location must be erased and repro-
grammed.
See Appendix C, Figure 17, Program Flowchart
and Pseudo Code, for the flowchart for using the
Program command.
Double Word Program Command
This feature is offered to improve the programming
throughput, writing a page of two adjacent words
in parallel.The two words must differ only for the
address A0. Programming should not be attempt-
ed when V
Three bus write cycles are necessary to issue the
Double Word Program command.
12/53
The second latches the block address in the
internal state machine and starts the Program/
Erase Controller.
The first bus cycle sets up the Program
command.
The second latches the Address and the Data to
be written and starts the Program/Erase
Controller.
The first bus cycle sets up the Double Word
Program Command.
The second bus cycle latches the Address and
the Data of the first word to be written.
The third bus cycle latches the Address and the
Data of the second word to be written and starts
the Program/Erase Controller.
PP
is not at V
PPH
.
IL
. As data integrity
IL
. As data
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to V
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 18, Double Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Double Word Program
command.
Quadruple Word Program Command
This feature is offered to improve the programming
throughput, writing a page of four adjacent words
in parallel.The four words must differ only for the
addresses A0 and A1. Programming should not be
attempted when V
Five bus write cycles are necessary to issue the
Quadruple Word Program command.
Read operations output the Status Register con-
tent after the programming has started. Program-
ming aborts if Reset goes to V
cannot be guaranteed when the program opera-
tion is aborted, the block containing the memory
location must be erased and reprogrammed.
See Appendix C, Figure 19, Quadruple Word Pro-
gram Flowchart and Pseudo Code, for the flow-
chart for using the Quadruple Word Program
command.
Clear Status Register Command
The Clear Status Register command can be used
to reset bits 1, 3, 4 and 5 in the Status Register to
‘0’. One bus write cycle is required to issue the
Clear Status Register command.
The bits in the Status Register do not automatical-
ly return to ‘0’ when a new Program or Erase com-
mand is issued. The error bits in the Status
Register should be cleared before attempting a
new Program or Erase command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to
pause a Program or Erase operation. One bus
write cycle is required to issue the Program/Erase
command and pause the Program/Erase control-
ler.
The first bus cycle sets up the Quadruple Word
Program Command.
The second bus cycle latches the Address and
the Data of the first word to be written.
The third bus cycle latches the Address and the
Data of the second word to be written.
The fourth bus cycle latches the Address and
the Data of the third word to be written.
The fifth bus cycle latches the Address and the
Data of the fourth word to be written and starts
the Program/Erase Controller.
PP
is not at V
IL
IL
PPH
. As data integrity
. As data integrity
.