lh28f008sc-v Sharp Microelectronics of the Americas, lh28f008sc-v Datasheet - Page 18
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lh28f008sc-v
Manufacturer Part Number
lh28f008sc-v
Description
8 M-bit 1 Mb X 8 Smart 5 Flash Memories
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LH28F008SC-V.pdf
(40 pages)
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FULL STATUS CHECK PROCEDURE
Read Status Register
Data and Address
Data (See Above)
Check if Desired
Status Register
Successful
Write 40H,
Full Status
Write Byte
Byte Write
Byte Write
Complete
Address
SR.7 =
SR.3 =
SR.1 =
SR.4 =
Read
Start
0
0
0
1
0
1
1
1
No
Byte Write
Device Protect Error
Suspend
V
Byte Write Error
PP
Fig. 4 Automated Byte Write Flowchart
Range Error
Suspend Byte
Write Loop
Yes
- 18 -
OPERATION
OPERATION COMMAND
Write
Write
Read
Standby
Standby
Standby
Standby
Repeat for subsequent byte writes.
SR full status check can be done after each byte write or after
a sequence of byte writes.
Write FFH after the last byte write operation to place device
in read array mode.
SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple locations are
written before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
BUS
BUS
COMMAND
Byte Write
Byte Write
Setup
Check SR.3
1 = V
Check SR.4
1 = Data Write Error
Data = 40H
Addr = Location to be Written
Data = Data to be Written
Addr = Location to be Written
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.1
1 = Device Protect Detect
RP# = V
Only required for systems
implementing lock-bit configuration
PP
Error Detect
IH
, Block Lock-Bit is Set
COMMENTS
COMMENTS
LH28F008SC-V/SCH-V
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