hyb18t512160bf-3 Qimonda, hyb18t512160bf-3 Datasheet - Page 39

• Manufacturer Part Number: hyb18t512160bf-3
• Description: 512-mbit Double-data-rate-two Sdram Ddr2 Sdram
• Manufacturer: Qimonda

1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Parameter
Mode register set command cycle
time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command
period
Read preamble
Read postamble
Active to active command period for
1KB page size products
Active to active command period for
2KB page size products
Internal Read to Precharge command
delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
Exit self-refresh to a non-read
command
Exit self-refresh to read command
Write command to DQS associated
clock edges
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
DDQ
= 1.8 V ± 0.1V;
V
DD
= 1.8 V ± 0.1 V.
V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
REF
MRD
OIT
QH
QHS
REFI
RFC
RP
RPRE
RPST
RRD
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
V
stabilizes. During the period before
TT
.
DDR2–800
2
0
t
—
—
—
105
t
0.9
0.4
7.5
10
7.5
0.35
0.4
15
7.5
2
8 – AL
2
t
200
RL – 1
Min.
HP
RP
RFC
–
+10
t
QHS
39
—
Max.
—
12
—
300
7.8
3.9
—
—
1.1
0.6
—
—
—
0.6
—
—
—
—
—
—
—
V
REF
DDR2–667
2
0
t
—
—
—
105
t
0.9
0.4
7.5
10
7.5
0.35
0.4
15
7.5
2
7 – AL
2
t
200
RL–1
512-Mbit Double-Data-Rate-Two SDRAM
Min.
HP
RP
RFC
stabilizes, CKE = 0.2 x
–
+10
t
QHS
Max.
—
12
—
340
7.8
3.9
—
—
1.1
0.6
—
—
—
—
0.6
—
—
—
—
—
—
—
HYB18T512[40/80/16]0BF
V
DDQ
Internet Data Sheet
is recognized as low.
Unit
nCK
ns
ps
ps
µs
µs
ns
ns
t
t
ns
ns
ns
t
t
ns
ns
nCK
nCK
nCK
ns
nCK
nCK
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Note
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