hyb18t512160bf-3 Qimonda, hyb18t512160bf-3 Datasheet - Page 6

• Manufacturer Part Number: hyb18t512160bf-3
• Description: 512-mbit Double-data-rate-two Sdram Ddr2 Sdram
• Manufacturer: Qimonda

2
This chapter contains the chip configuration.
2.1
The chip configuration of a DDR2 SDRAM is listed by function in
explained in
Rev. 1.2, 2007-11
03292006-YBYM-WG0Z
Ball#
Clock Signals ×4 /×8 Organizations
E8
F8
F2
Control Signals ×4 /×8 Organizations
F7
G7
F3
G8
Address Signals ×4 /×8 Organizations
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
Table 7
Name
CK
CK
CKE
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
and
Configuration
Configuration for TFBGA-60
Table 8
Ball
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
respectively. The ball numbering for the FBGA package is depicted in figures.
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Clock Signal CK, CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Chip Select
Bank Address Bus 1:0
Address Signal 13:0, Address Signal 10/Autoprecharge
6
Table
6. The abbreviations used in the Ball# columns are
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512[40/80/16]0BF
Internet Data Sheet
Configuration
TABLE 3