m29f040 STMicroelectronics, m29f040 Datasheet - Page 10

• Manufacturer Part Number: m29f040
• Description: 4 Mbit 512kb X8, Uniform Block Single Supply Flash Memory
• Manufacturer: STMicroelectronics

M29F040
Read Block Protection (RBP) instruction. The
use of Read Electronic Signature (RSIG) command
also allows access to the Block Protection status
verify. After giving the RSIG command, A0 and A6
are set to V
A18 define the block of the block to be verified. A
read in these conditions will output a 01h if block is
protected and a 00h if block is not protected.
This Read Block Protection is the only valid way to
check the protection status of a block. Neverthe-
less, it must not be used during the Block Protection
phase as a method to verify the block protection.
Please refer to Block Protection paragraph.
Chip Erase (CE) instruction. This instruction uses
six write cycles. The Erase Set-up command 80h
is written to address 5555h on third cycle after the
two coded cycles. The Chip Erase Confirm com-
10/31
Table 11. DC Characteristics
(T
Symbol
A
V
I
I
I
I
I
V
V
= 0 to 70 C, –20 to 85 C, –40 to 85 C or –40 to 125 C; V
V
V
I
V
CC1
CC2
CC3
CC4
CC5
I
I
LO
LKO
OH
ID
LI
OL
IH
ID
IL
Input Leakage Current
Output Leakage Current
Supply Current (Read)
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Supply Current (Program or Erase)
Supply Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
Output High Voltage CMOS
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
Supply Voltage (Erase and
Program lock-out)
IL
with A1 at V
Parameter
IH
, while A16, A17 and
E = V
Chip Erase in progress
0V
Test Condition
E = V
Byte Program,
0V
IL
I
I
I
, G = V
OH
OH
OH
Block Erase
I
OL
A9 = V
E = V
= –100 A
V
= –2.5mA
= –2.5mA
mand 10h is written at address 5555h on sixth cycle
after another two coded cycles. If the second com-
mand given is not an erase confirm or if the coded
cycles are wrong, the instruction aborts and the
device is reset to Read Array. It is not necessary to
program the array with 00h first as the P/E.C. will
automatically do this before erasing to FFh. Read
operations after the sixth rising edge of W or E
output the status register bits. During the execu-
tion of the erase by the P/E.C. the memory accepts
only the Reset (RST) command. Read of Data
Polling bit DQ7 returns ’0’, then ’1’ on completion.
The Toggle Bit DQ6 toggles during erase operation
and stops when erase is completed. After comple-
tion the Status Register bit DQ5 returns ’1’ if there
has been an Erase Failure because the erasure
has not been verified even after the maximum
number of erase cycles have been executed.
= 10mA
V
CC
OUT
IN
IH
IH
, f = 6MHz
ID
0.2V
V
V
CC
CC
CC
= 5V
10%)
V
0.85 V
CC
–0.5
11.5
Min
2.4
3.2
2
–0.4
CC
V
CC
Max
0.45
12.5
0.8
4.2
15
50
20
40
50
1
+ 0.5
1
1
Unit
mA
mA
mA
mA
V
V
V
V
V
V
V
V
A
A
A
A