m29f040 STMicroelectronics, m29f040 Datasheet - Page 11

• Manufacturer Part Number: m29f040
• Description: 4 Mbit 512kb X8, Uniform Block Single Supply Flash Memory
• Manufacturer: STMicroelectronics

Table 12A. Read AC Characteristics
(T
Notes: 1. Sampled only, not 100% tested.
Block Erase (BE) instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two coded cycles. The Block
Erase Confirm command 30h is written on sixth
cycle after another two coded cycles. During the
input of the second command an address within
the block to be erased is given and latched into the
memory. Additional Block Erase confirm com-
mands and block addresses can be written sub-
sequently to erase other blocks in parallel, without
further coded cycles. The erase will start after an
Erase timeout period of about 100 s. Thus, addi-
tional Block Erase commands must be given within
this delay. The input of a new Block Erase com-
mand will restart the timeout period. The status of
the internal timer can be monitored through the
level of DQ3, if DQ3 is ’0’ the Block Erase Com-
mand has been given and the timeout is running, if
DQ3 is ’1’, the timeout has expired and the P/E.C
Symbol
t
t
t
t
t
t
GHQZ
A
ELQX
ELQV
GLQX
GLQV
EHQZ
t
t
t
t
t
GHQX
AVQV
EHQX
AXQX
AVAV
= 0 to 70 C, –20 to 85 C, –40 to 85 C or –40 to 125 C)
2. G may be delayed by up to t
3. The temperature range –40 to 125 C is guaranteed at 70ns with High Speed Interface test condition and V
(1)
(2)
(1)
(2)
(1)
(1)
t
t
Alt
t
t
t
t
t
ACC
t
t
t
t
OLZ
RC
OE
OH
OH
OH
CE
HZ
DF
LZ
Address Valid to Next Address Valid
Address Valid to Output Valid
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output
Transition
Output Enable Low to Output Valid
Chip Enable High to Output
Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output
Transition
Output Enable High to Output Hi-Z
Address Transition to Output
Transition
Parameter
ELQV
- t
GLQV
after the falling edge of E without increasing t
Test Condition
E = V
E = V
E = V
is erasing the block(s). Before and during Erase
timeout, any command different from 30h will abort
the instruction and reset the device to read array
mode. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register bits.
During the execution of the erase by the P/E.C., the
memory accepts only the ES (Erase Suspend) and
RST (Reset) instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle Bit DQ6 toggles
during the erase operation. It stops when erase is
completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure because erasure has not completed even
after the maximum number of erase cycles have
been executed. In this case, it will be necessary to
input a Reset (RST) to the command interface in
order to reset the P/E.C.
G = V
G = V
E = V
E = V
G = V
G = V
E = V
E = V
IL
IL
IL
, G = V
, G = V
, G = V
(3)
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
IL
V
Min
CC
70
20
0
0
0
0
Standard
Interface
ELQV
= 5V
-70
.
Max
70
70
30
20
20
M29F040
5%
V
CC
Min
90
20
0
0
0
0
Standard
Interface
CC
= 5V
-90
= 5V
Max
90
90
35
20
20
10%
M29F040
5%.
Unit
11/31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns