m29f200t STMicroelectronics, m29f200t Datasheet - Page 13

• Manufacturer Part Number: m29f200t
• Description: 2 Mbit 256kb X8 Or 128kb X16, Boot Block Single Supply Flash Memory
• Manufacturer: STMicroelectronics

Table 13. DC Characteristics
(T
Note: 1. Sampled only, not 100% tested.
confirm or if the Coded cycles are wrong, the
instruction aborts, and the device is reset to Read
Array. It is not necessary to program the block with
00h as the P/E.C. will do this automatically before
to erasing to FFh. Read operations after the sixth
rising edge of W or E output the status register
status bits.
During the executionof the erase by the P/E.C., the
memory accepts only the Erase Suspend ES and
Read/Reset RD instructions. Data Polling bit DQ7
returns ’0’ while the erasure is in progress and ’1’
when it has completed. The Toggle bit DQ2 and
DQ6 toggle during the erase operation. They stop
when erase is completed. After completion the
Status Register bit DQ5 returns’1’ if there has been
an erase failure. In such a situation, the Toggle bit
DQ2 can be used to determine which block is not
correctly erased. In the case of erase failure, a
Read/Reset RD instruction is necessary in order to
reset the P/E.C.
Symbol
A
I
CC4
V
I
I
I
I
V
V
V
V
= 0 to 70 C, –40 to 85 C or –40 to 125 C; V
I
CC1
CC1
CC2
CC3
V
I
I
LO
LKO
LI
OH
ID
OL
IH
ID
IL
(1)
Input Leakage Current
Output Leakage Current
Supply Current (Read) TTL Byte
Supply Current (Read) TTL Word
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Supply Current (Program or Erase)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
Output High Voltage CMOS
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
Supply Voltage (Erase and
Program lock-out)
Parameter
E = V
E = V
Byte program, Block or
Chip Erase in progress
CC
0V
Test Condition
E = V
0V
IL
IL
= 5V
I
I
, G = V
, G = V
I
OH
OH
OL
A9 = V
E = V
= –100 A
V
= –2.5mA
Chip Erase (CE) Instruction. Thisinstructionuses
six write cycles. The Erase Set-up command 80h
is written to address AAAAh in the Byte-wide con-
figuration or the address 5555h in the Word-wide
configurationon the third cycle after the two Coded
cycles. The Chip Erase Confirm command 10h is
similarly written on the sixth cycle after anothertwo
Coded cycles. If the second command given is not
an erase confirm or if the Coded cycles are wrong,
the instruction aborts and the device is reset to
Read Array. It is not necessaryto programthe array
with 00h first as the P/E.C. will automaticallydo this
before erasing it to FFh. Read operations after the
sixth rising edge of W or E output the Status
Register bits. During the execution of the erase by
the P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’
on completion. The Toggle bits DQ2 and DQ6
toggle during erase operation and stop when erase
is completed. After completion the Status Register
bit DQ5 returns ’1’ if there has been an Erase
Failure.
= 5.8mA
V
CC
OUT
IN
IH
IH
10%)
IH
, f = 6MHz
, f = 6MHz
ID
0.2V
V
V
CC
CC
V
CC
–0.5
Min
11.0
2.4
3.2
2
–0.4V
M29F200T, M29F200B
V
CC
Max
0.45
12.0
100
100
0.8
4.2
20
20
20
1
+ 0.5
1
1
Unit
mA
mA
mA
mA
V
V
V
V
V
V
V
13/33
A
A
A
A