m29f200t STMicroelectronics, m29f200t Datasheet - Page 6

• Manufacturer Part Number: m29f200t
• Description: 2 Mbit 256kb X8 Or 128kb X16, Boot Block Single Supply Flash Memory
• Manufacturer: STMicroelectronics

M29F200T, M29F200B
Ready/Busy Output (RB). Ready/Busy is an
open-drainoutput and gives the internalstate of the
P/E.C. of the device. When RB is Low, the device
is Busy with a Program or Erase operation and it
will not accept any additional program or erase
instructions except the Erase Suspend instruction.
WhenRB is High, the device is ready for any Read,
Program or Erase operation. The RB will also be
High when the memory is put in Erase Suspend or
Standby modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is acheived by pulling RP to
V
given, if the memory is in Read or Standby modes,
it will be available for new operations in 50ns after
the rising edge of RP. If the memory is in Erase,
Erase Suspend or Program modes the reset will
take 10 s during which the RB signal will be held
at V
by the rising edge of RB. A hardware reset during
an Eraseor Programoperation will corrupt the data
being programmed or the sector(s) being erased.
Temporary block unprotection is made by holding
RP at V
blocks can be programmed or erased. The transi-
tion of RP from V
When RP is returned from V
temporarily unprotected will be again protected.
V
operations (Read, Program and Erase).
V
measurements.
DEVICE OPERATIONS
See Tables 4, 5 and 6.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the
memory.
Write. Write operationsare used to give Instruction
Commands to the memory or to latch input data to
be programmed. A write operationis initiated when
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whicheveroccurs last.
Commands and Input Data are latched on the rising
edge of W or E whichever occurs first.
6/33
IL
CC
SS
IL
for at least 500ns. When the reset pulse is
Ground. V
. The end of the memory reset will be indicated
Supply Voltage. The power supply for all
ID
. In this condition previously protected
SS
IH
is the reference for all voltage
to V
ID
must slower than 500ns.
ID
to V
IH
all blocks
Output Disable. The data outputs are high imped-
ance when the Output Enable G is High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
Automatic Standby. After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumption is reduced to the CMOS
standby value, while outputs still drive the bus.
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for STMi-
croelectronics is 20h, the device code is D3h for the
M29F200T (Top Boot) and D4h for the M29F200B
(Bottom Boot). These codes allow programming
equipment or applications to automatically match
their interface to the characteristics of the
M29F200. The Electronic Signature is output by a
Read operation when the voltage applied to A9 is
at V
turer code is output when the Address input A0 is
Low and the device code when this input is High.
Other Address inputs are ignored. The codes are
output on DQ0-DQ7.
The Electronic Signature can also be read, without
raising A9 to V
tion AS. If the Byte-wide configuration is selected
the codes are output on DQ0-DQ7with DQ8-DQ14
at High impedance; if the Word-wide configuration
is selected the codes are output on DQ0-DQ7 with
DQ8-DQ15 at 00h.
Block Protection. Each block can be separately
protected against Program or Erase on program-
ming equipment. Block protection provides addi-
tional data security, as it disables all program or
erase operations.This mode is activatedwhen both
A9 and G are raised to V
block is applied on A12-A16. The Block Protection
algorithm is shown in Figure 14. Block protection is
initiated on the edge of W falling to V
a delay of 100 s, the edge of W rising to V
the protection operations. Block protection verify is
achieved by bringing G, E, A0and A6 to V
to V
conditions, reading the data output will yield 01h if
the block defined by the inputs on A12-A16 is
protected. Any attempt to program or erase a pro-
tected block will be ignored by the device.
IH
ID
, while W is at V
and address input A1 is Low. The manufac-
ID
, by giving the memory the Instruc-
IH
and A9 at V
ID
and an address in the
ID
. Under these
IL
. Then after
IL
IH
and A1
ends